Lines Matching refs:PredReg
60 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); in ReplaceTailWithBranchTo()
108 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; in isLegalToSplitMBBAt()
180 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate() argument
195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
217 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
403 unsigned PredReg; in rewriteT2FrameIndex() local
404 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { in rewriteT2FrameIndex()
575 unsigned PredReg = 0; in scheduleTwoAddrSource() local
576 ARMCC::CondCodes CC = getInstrPredicate(UseMI, PredReg); in scheduleTwoAddrSource()
577 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in scheduleTwoAddrSource()
592 ARMCC::CondCodes NCC = getInstrPredicate(NMI, PredReg); in scheduleTwoAddrSource()
609 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getITInstrPredicate() argument
613 return getInstrPredicate(MI, PredReg); in getITInstrPredicate()