Lines Matching refs:MI
152 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
156 bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
159 bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
165 bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
172 bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
252 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry, in VerifyPredAndCC() argument
282 if (!HasImplicitCPSRDef(MI->getDesc())) in VerifyPredAndCC()
294 static bool VerifyLowRegs(MachineInstr *MI) { in VerifyLowRegs() argument
295 unsigned Opc = MI->getOpcode(); in VerifyLowRegs()
301 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in VerifyLowRegs()
302 const MachineOperand &MO = MI->getOperand(i); in VerifyLowRegs()
326 Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, in ReduceLoadStore() argument
345 if (MI->getOperand(1).getReg() == ARM::SP) { in ReduceLoadStore()
379 unsigned BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore()
386 for (unsigned i = 4; i < MI->getNumOperands(); ++i) { in ReduceLoadStore()
387 if (MI->getOperand(i).getReg() == BaseReg) { in ReduceLoadStore()
401 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore()
415 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore()
435 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
436 OffsetKill = MI->getOperand(2).isKill(); in ReduceLoadStore()
438 if (MI->getOperand(3).getImm()) in ReduceLoadStore()
445 OffsetImm = MI->getOperand(2).getImm(); in ReduceLoadStore()
454 DebugLoc dl = MI->getDebugLoc(); in ReduceLoadStore()
455 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); in ReduceLoadStore()
457 MIB.addOperand(MI->getOperand(0)); in ReduceLoadStore()
458 MIB.addOperand(MI->getOperand(1)); in ReduceLoadStore()
470 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum) in ReduceLoadStore()
471 MIB.addOperand(MI->getOperand(OpNum)); in ReduceLoadStore()
474 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in ReduceLoadStore()
477 MIB.setMIFlags(MI->getFlags()); in ReduceLoadStore()
479 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); in ReduceLoadStore()
481 MBB.erase_instr(MI); in ReduceLoadStore()
487 Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI, in ReduceSpecial() argument
491 unsigned Opc = MI->getOpcode(); in ReduceSpecial()
495 if (MI->getOperand(1).getReg() != ARM::SP) { in ReduceSpecial()
496 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) in ReduceSpecial()
498 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop); in ReduceSpecial()
501 unsigned Imm = MI->getOperand(2).getImm(); in ReduceSpecial()
507 if (!isARMLowRegister(MI->getOperand(0).getReg())) in ReduceSpecial()
509 if (MI->getOperand(3).getImm() != ARMCC::AL) in ReduceSpecial()
511 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial()
513 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) in ReduceSpecial()
516 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), in ReduceSpecial()
518 .addOperand(MI->getOperand(0)) in ReduceSpecial()
519 .addOperand(MI->getOperand(1)) in ReduceSpecial()
524 MIB.setMIFlags(MI->getFlags()); in ReduceSpecial()
526 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB); in ReduceSpecial()
528 MBB.erase_instr(MI); in ReduceSpecial()
533 if (Entry.LowRegs1 && !VerifyLowRegs(MI)) in ReduceSpecial()
536 if (MI->mayLoad() || MI->mayStore()) in ReduceSpecial()
537 return ReduceLoadStore(MBB, MI, Entry); in ReduceSpecial()
544 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
548 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) in ReduceSpecial()
553 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop); in ReduceSpecial()
564 if (MI->getOperand(2).getImm() == 0) in ReduceSpecial()
565 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop); in ReduceSpecial()
570 if (MI->getOperand(1).isImm()) in ReduceSpecial()
571 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop); in ReduceSpecial()
581 if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, CPSRDef, IsSelfLoop)) in ReduceSpecial()
583 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop); in ReduceSpecial()
590 Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI, in ReduceTo2Addr() argument
598 unsigned Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr()
599 unsigned Reg1 = MI->getOperand(1).getReg(); in ReduceTo2Addr()
601 if (MI->getOpcode() == ARM::t2MUL) { in ReduceTo2Addr()
602 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr()
613 MachineInstr *CommutedMI = TII->commuteInstruction(MI); in ReduceTo2Addr()
620 if (!TII->findCommutedOpIndices(MI, CommOpIdx1, CommOpIdx2) || in ReduceTo2Addr()
621 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
623 MachineInstr *CommutedMI = TII->commuteInstruction(MI); in ReduceTo2Addr()
630 unsigned Imm = MI->getOperand(2).getImm(); in ReduceTo2Addr()
635 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr()
643 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceTo2Addr()
655 const MCInstrDesc &MCID = MI->getDesc(); in ReduceTo2Addr()
658 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceTo2Addr()
659 if (HasCC && MI->getOperand(NumOps-1).isDead()) in ReduceTo2Addr()
662 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead)) in ReduceTo2Addr()
668 canAddPseudoFlagDep(CPSRDef, MI, IsSelfLoop)) in ReduceTo2Addr()
672 DebugLoc dl = MI->getDebugLoc(); in ReduceTo2Addr()
673 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); in ReduceTo2Addr()
674 MIB.addOperand(MI->getOperand(0)); in ReduceTo2Addr()
684 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { in ReduceTo2Addr()
689 MIB.addOperand(MI->getOperand(i)); in ReduceTo2Addr()
693 MIB.setMIFlags(MI->getFlags()); in ReduceTo2Addr()
695 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); in ReduceTo2Addr()
697 MBB.erase_instr(MI); in ReduceTo2Addr()
703 Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI, in ReduceToNarrow() argument
714 const MCInstrDesc &MCID = MI->getDesc(); in ReduceToNarrow()
718 const MachineOperand &MO = MI->getOperand(i); in ReduceToNarrow()
735 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceToNarrow()
749 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceToNarrow()
750 if (HasCC && MI->getOperand(NumOps-1).isDead()) in ReduceToNarrow()
753 if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead)) in ReduceToNarrow()
759 canAddPseudoFlagDep(CPSRDef, MI, IsSelfLoop)) in ReduceToNarrow()
763 DebugLoc dl = MI->getDebugLoc(); in ReduceToNarrow()
764 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); in ReduceToNarrow()
765 MIB.addOperand(MI->getOperand(0)); in ReduceToNarrow()
775 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { in ReduceToNarrow()
789 const MachineOperand &MO = MI->getOperand(i); in ReduceToNarrow()
800 MIB.setMIFlags(MI->getFlags()); in ReduceToNarrow()
802 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); in ReduceToNarrow()
804 MBB.erase_instr(MI); in ReduceToNarrow()
809 static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR) { in UpdateCPSRDef() argument
811 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { in UpdateCPSRDef()
812 const MachineOperand &MO = MI.getOperand(i); in UpdateCPSRDef()
826 static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) { in UpdateCPSRUse() argument
827 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { in UpdateCPSRUse()
828 const MachineOperand &MO = MI.getOperand(i); in UpdateCPSRUse()
859 MachineInstr *MI = &*MII; in ReduceMBB() local
860 if (MI->isBundle()) { in ReduceMBB()
861 BundleMI = MI; in ReduceMBB()
865 LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR); in ReduceMBB()
867 unsigned Opcode = MI->getOpcode(); in ReduceMBB()
873 if (ReduceSpecial(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) { in ReduceMBB()
876 MI = &*I; in ReduceMBB()
883 ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) { in ReduceMBB()
886 MI = &*I; in ReduceMBB()
892 ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) { in ReduceMBB()
895 MI = &*I; in ReduceMBB()
900 if (NextMII != E && MI->isInsideBundle() && !NextMII->isInsideBundle()) { in ReduceMBB()
913 LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR, DefCPSR); in ReduceMBB()
914 if (MI->isCall()) { in ReduceMBB()
920 CPSRDef = MI; in ReduceMBB()