Lines Matching refs:access
25 , InstrStage<1,[MA]> // one cycle in memory access stage
40 , InstrStage<1,[MA]> // one cycle in memory access stage
48 // stages except the memory access stage, which takes 31 cycles. The two
50 // after the memory access stage.
55 , InstrStage<31,[MA]> // 31 cycles in memory access stage
65 // ready after the memory access stage.
70 , InstrStage<1,[MA]> // one cycle in memory access stage
83 , InstrStage<1,[MA]> // one cycle in memory access stage
94 , InstrStage<1,[MA]> // one cycle in memory access stage
107 , InstrStage<1,[MA]> // one cycle in memory access stage
114 // except the memory access stage, which takes two cycles. The source
120 , InstrStage<2,[MA]> // two cycles in memory access stage
127 // the pipeline stages except the memory access stage, which takes two
134 , InstrStage<2,[MA]> // two cycles in memory access stage
142 // each of the pipeline stages except the memory access stage, which takes 26
149 , InstrStage<26,[MA]> // 26 cycles in memory access stage
157 // to execute in each of the pipeline stages except the memory access stage,
164 , InstrStage<3,[MA]> // three cycles in memory access stage
171 // to execute in each of the pipeline stages except the memory access stage,
178 , InstrStage<2,[MA]> // two cycles in memory access stage
185 // each of the pipeline stages except the memory access stage, which takes 25
192 , InstrStage<25,[MA]> // 25 cycles in memory access stage
205 , InstrStage<1,[MA]> // one cycle in memory access stage
219 , InstrStage<1,[MA]> // one cycle in memory access stage
233 , InstrStage<1,[MA]> // one cycle in memory access stage
247 , InstrStage<1,[MA]> // one cycle in memory access stage
262 , InstrStage<1,[MA]> // one cycle in memory access stage