Lines Matching refs:X86
78 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; in is64BitMode()
81 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit)); in SwitchMode()
458 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI; in isSrcOp()
461 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) && in isSrcOp()
468 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI; in isDstOp()
471 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::ES) && in isDstOp()
506 if (RegNo == X86::RIZ || in ParseRegister()
507 X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) || in ParseRegister()
517 RegNo = X86::ST0; in ParseRegister()
531 case 0: RegNo = X86::ST0; break; in ParseRegister()
532 case 1: RegNo = X86::ST1; break; in ParseRegister()
533 case 2: RegNo = X86::ST2; break; in ParseRegister()
534 case 3: RegNo = X86::ST3; break; in ParseRegister()
535 case 4: RegNo = X86::ST4; break; in ParseRegister()
536 case 5: RegNo = X86::ST5; break; in ParseRegister()
537 case 6: RegNo = X86::ST6; break; in ParseRegister()
538 case 7: RegNo = X86::ST7; break; in ParseRegister()
555 case '0': RegNo = X86::DR0; break; in ParseRegister()
556 case '1': RegNo = X86::DR1; break; in ParseRegister()
557 case '2': RegNo = X86::DR2; break; in ParseRegister()
558 case '3': RegNo = X86::DR3; break; in ParseRegister()
559 case '4': RegNo = X86::DR4; break; in ParseRegister()
560 case '5': RegNo = X86::DR5; break; in ParseRegister()
561 case '6': RegNo = X86::DR6; break; in ParseRegister()
562 case '7': RegNo = X86::DR7; break; in ParseRegister()
757 if (RegNo == X86::EIZ || RegNo == X86::RIZ) { in ParseATTOperand()
846 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) { in ParseMemOperand()
920 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) && in ParseMemOperand()
921 !X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) && in ParseMemOperand()
922 IndexReg != X86::RIZ) { in ParseMemOperand()
926 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) && in ParseMemOperand()
927 !X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) && in ParseMemOperand()
928 IndexReg != X86::EIZ){ in ParseMemOperand()
1101 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) { in ParseInstruction()
1114 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) { in ParseInstruction()
1145 if (reg == X86::AL && (isLods || Name == "lodsb")) in ParseInstruction()
1147 else if (reg == X86::AX && (isLods || Name == "lodsw")) in ParseInstruction()
1149 else if (reg == X86::EAX && (isLods || Name == "lodsl")) in ParseInstruction()
1151 else if (reg == X86::RAX && (isLods || Name == "lodsq")) in ParseInstruction()
1175 if (reg == X86::AL && (isStos || Name == "stosb")) in ParseInstruction()
1177 else if (reg == X86::AX && (isStos || Name == "stosw")) in ParseInstruction()
1179 else if (reg == X86::EAX && (isStos || Name == "stosl")) in ParseInstruction()
1181 else if (reg == X86::RAX && (isStos || Name == "stosq")) in ParseInstruction()
1241 case X86::AND16i16: { in processInstruction()
1247 TmpInst.setOpcode(X86::AND16ri8); in processInstruction()
1248 TmpInst.addOperand(MCOperand::CreateReg(X86::AX)); in processInstruction()
1249 TmpInst.addOperand(MCOperand::CreateReg(X86::AX)); in processInstruction()
1254 case X86::AND32i32: { in processInstruction()
1260 TmpInst.setOpcode(X86::AND32ri8); in processInstruction()
1261 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX)); in processInstruction()
1262 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX)); in processInstruction()
1267 case X86::AND64i32: { in processInstruction()
1273 TmpInst.setOpcode(X86::AND64ri8); in processInstruction()
1274 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1275 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1280 case X86::XOR16i16: { in processInstruction()
1286 TmpInst.setOpcode(X86::XOR16ri8); in processInstruction()
1287 TmpInst.addOperand(MCOperand::CreateReg(X86::AX)); in processInstruction()
1288 TmpInst.addOperand(MCOperand::CreateReg(X86::AX)); in processInstruction()
1293 case X86::XOR32i32: { in processInstruction()
1299 TmpInst.setOpcode(X86::XOR32ri8); in processInstruction()
1300 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX)); in processInstruction()
1301 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX)); in processInstruction()
1306 case X86::XOR64i32: { in processInstruction()
1312 TmpInst.setOpcode(X86::XOR64ri8); in processInstruction()
1313 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1314 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1319 case X86::OR16i16: { in processInstruction()
1325 TmpInst.setOpcode(X86::OR16ri8); in processInstruction()
1326 TmpInst.addOperand(MCOperand::CreateReg(X86::AX)); in processInstruction()
1327 TmpInst.addOperand(MCOperand::CreateReg(X86::AX)); in processInstruction()
1332 case X86::OR32i32: { in processInstruction()
1338 TmpInst.setOpcode(X86::OR32ri8); in processInstruction()
1339 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX)); in processInstruction()
1340 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX)); in processInstruction()
1345 case X86::OR64i32: { in processInstruction()
1351 TmpInst.setOpcode(X86::OR64ri8); in processInstruction()
1352 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1353 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1358 case X86::CMP16i16: { in processInstruction()
1364 TmpInst.setOpcode(X86::CMP16ri8); in processInstruction()
1365 TmpInst.addOperand(MCOperand::CreateReg(X86::AX)); in processInstruction()
1370 case X86::CMP32i32: { in processInstruction()
1376 TmpInst.setOpcode(X86::CMP32ri8); in processInstruction()
1377 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX)); in processInstruction()
1382 case X86::CMP64i32: { in processInstruction()
1388 TmpInst.setOpcode(X86::CMP64ri8); in processInstruction()
1389 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1394 case X86::ADD16i16: { in processInstruction()
1400 TmpInst.setOpcode(X86::ADD16ri8); in processInstruction()
1401 TmpInst.addOperand(MCOperand::CreateReg(X86::AX)); in processInstruction()
1402 TmpInst.addOperand(MCOperand::CreateReg(X86::AX)); in processInstruction()
1407 case X86::ADD32i32: { in processInstruction()
1413 TmpInst.setOpcode(X86::ADD32ri8); in processInstruction()
1414 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX)); in processInstruction()
1415 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX)); in processInstruction()
1420 case X86::ADD64i32: { in processInstruction()
1426 TmpInst.setOpcode(X86::ADD64ri8); in processInstruction()
1427 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1428 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1433 case X86::SUB16i16: { in processInstruction()
1439 TmpInst.setOpcode(X86::SUB16ri8); in processInstruction()
1440 TmpInst.addOperand(MCOperand::CreateReg(X86::AX)); in processInstruction()
1441 TmpInst.addOperand(MCOperand::CreateReg(X86::AX)); in processInstruction()
1446 case X86::SUB32i32: { in processInstruction()
1452 TmpInst.setOpcode(X86::SUB32ri8); in processInstruction()
1453 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX)); in processInstruction()
1454 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX)); in processInstruction()
1459 case X86::SUB64i32: { in processInstruction()
1465 TmpInst.setOpcode(X86::SUB64ri8); in processInstruction()
1466 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1467 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX)); in processInstruction()
1492 Inst.setOpcode(X86::WAIT); in MatchAndEmitInstruction()