Lines Matching refs:ZERO_EXTEND
765 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); in X86TargetLowering()
1225 setTargetDAGCombine(ISD::ZERO_EXTEND); in X86TargetLowering()
1619 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) in getTypeForExtArgOrReturn()
2232 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); in LowerCall()
4672 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, in LowerBuildVectorv16i8()
4676 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); in LowerBuildVectorv16i8()
5136 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); in LowerBUILD_VECTOR()
9338 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
9666 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
10065 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); in LowerFLT_ROUNDS_()
10078 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); in LowerCTLZ()
10113 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); in LowerCTLZ_ZERO_UNDEF()
13222 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) in PerformEXTRACT_VECTOR_ELTCombine()
13460 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); in PerformSELECTCombine()
13474 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, in PerformSELECTCombine()
13509 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), in PerformSELECTCombine()
13624 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); in PerformCMOVCombine()
13641 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, in PerformCMOVCombine()
13678 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), in PerformCMOVCombine()
13777 N00.getOpcode() == ISD::ZERO_EXTEND) && in PerformSHLCombine()
13891 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); in PerformShiftCombine()
13973 case ISD::ZERO_EXTEND: in CMPEQCombine()
14999 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) in OptimizeConditionalInDecrement()
15109 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget); in PerformDAGCombine()
15147 case ISD::ZERO_EXTEND: in isTypeDesirableForOp()
15191 case ISD::ZERO_EXTEND: in IsDesirableToPromoteOp()