Lines Matching refs:src2
48 VR128:$src2),
49 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
50 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2))]>, VEX;
52 memop:$src2),
53 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
55 (bitconvert mem_cpat:$src2)))]>, VEX;
87 (ins VR128:$src1, VR128:$src2),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
89 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2))]>, VEX_4VOp3;
91 (ins VR128:$src1, f128mem:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
94 (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))]>,
97 (ins f128mem:$src1, VR128:$src2),
98 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
100 (Int (bitconvert (memopv2i64 addr:$src1)), VR128:$src2))]>,
122 (ins VR128:$src1, i8imm:$src2),
123 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
127 (ins f128mem:$src1, i8imm:$src2),
128 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
143 (ins VR128:$src1, VR128:$src2, VR128:$src3),
145 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
147 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_4V, VEX_I8IMM;
149 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
151 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
153 (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
176 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
178 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
180 (VT (OpNode VR128:$src1, VR128:$src2, imm:$src3)))]>, VEX_4V;
182 (ins VR128:$src1, f128mem:$src2, i8imm:$src3),
184 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
186 (VT (OpNode VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
204 (ins VR128:$src1, VR128:$src2, VR128:$src3),
206 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
207 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, VR128:$src3))]>,
210 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
212 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
214 (Int VR128:$src1, VR128:$src2,
218 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
220 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
222 (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
234 (ins VR256:$src1, VR256:$src2, VR256:$src3),
236 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
237 [(set VR256:$dst, (Int VR256:$src1, VR256:$src2, VR256:$src3))]>,
240 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
242 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
244 (Int VR256:$src1, VR256:$src2,
248 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
250 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
252 (Int VR256:$src1, (bitconvert (memopv4i64 addr:$src2)),
264 (ins VR128:$src1, VR128:$src2, VR128:$src3, i8imm:$src4),
266 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
268 (Int128 VR128:$src1, VR128:$src2, VR128:$src3, imm:$src4))]>;
270 (ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4),
272 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
274 (Int128 VR128:$src1, VR128:$src2, (ld_128 addr:$src3), imm:$src4))]>,
277 (ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4),
279 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
281 (Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>;
283 (ins VR256:$src1, VR256:$src2, VR256:$src3, i8imm:$src4),
285 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
287 (Int256 VR256:$src1, VR256:$src2, VR256:$src3, imm:$src4))]>;
289 (ins VR256:$src1, VR256:$src2, f256mem:$src3, i8imm:$src4),
291 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
293 (Int256 VR256:$src1, VR256:$src2, (ld_256 addr:$src3), imm:$src4))]>,
296 (ins VR256:$src1, f256mem:$src2, VR256:$src3, i8imm:$src4),
298 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
300 (Int256 VR256:$src1, (ld_256 addr:$src2), VR256:$src3, imm:$src4))]>;