Lines Matching refs:x01
8 name:x01 type:mandatory default:0x01
9 0x01 No unit mask
18 name:arith type:bitmask default:0x01
19 0x01 cycles_div_busy Cycles the divider is busy
21 name:baclear type:bitmask default:0x01
22 0x01 clear BACLEAR asserted, regardless of cause
24 name:bpu_clears type:bitmask default:0x01
25 0x01 early Early Branch Prediction Unit clears
28 0x01 cond Conditional branch instructions executed
39 0x01 conditional Retired conditional branch instructions (Precise Event)
43 0x01 cond Mispredicted conditional branches executed
54 0x01 conditional Mispredicted conditional retired branches (Precise Event)
57 name:cache_lock_cycles type:bitmask default:0x01
58 0x01 l1d_l2 Cycles L1D and L2 locked
62 0x01 ref_p Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)
63 name:dtlb_load_misses type:bitmask default:0x01
64 0x01 any DTLB load misses
70 name:dtlb_misses type:bitmask default:0x01
71 0x01 any DTLB misses
77 name:fp_assist type:bitmask default:0x01
78 0x01 all X87 Floating point assists (Precise Event)
81 name:fp_comp_ops_exe type:bitmask default:0x01
82 0x01 x87 Computational floating-point operations executed
91 0x01 to_fp Transitions from MMX to Floating Point instructions
95 0x01 lcp Length Change Prefix stall cycles
100 name:inst_retired type:bitmask default:0x01
101 0x01 any_p Instructions retired (Programmable counter and Precise Event)
104 name:itlb_misses type:bitmask default:0x01
105 0x01 any ITLB miss
109 name:l1d type:bitmask default:0x01
110 0x01 repl L1 data cache lines allocated
114 name:l1d_prefetch type:bitmask default:0x01
115 0x01 requests L1D hardware prefetch requests
119 0x01 i_state L1 writebacks to L2 in I state (misses)
124 name:l1i type:bitmask default:0x01
125 0x01 hits L1I instruction fetch hits
130 0x01 demand_i_state L2 data demand loads in I state (misses)
146 0x01 demand_clean L2 lines evicted by a demand request
151 name:l2_rqsts type:bitmask default:0x01
152 0x01 ld_hit L2 load hits
167 0x01 load L2 Load transactions
175 name:l2_write type:bitmask default:0x01
176 0x01 rfo_i_state L2 demand store RFOs in I state (misses)
188 0x01 rs Loads dispatched that bypass the MOB
192 name:longest_lat_cache type:bitmask default:0x01
193 0x01 miss Longest latency cache miss
195 name:machine_clears type:bitmask default:0x01
196 0x01 cycles Cycles machine clear asserted
199 name:mem_inst_retired type:bitmask default:0x01
200 0x01 loads Instructions retired which contains a load (Precise Event)
203 name:mem_load_retired type:bitmask default:0x01
204 0x01 l1d_hit Retired loads that hit the L1 data cache (Precise Event)
218 0x01 demand_read_data Offcore demand data read requests
226 0x01 demand_read_data Outstanding offcore demand data reads
231 0x01 flags Flag stall cycles
236 name:resource_stalls type:bitmask default:0x01
237 0x01 any Resource related stall cycles
245 name:simd_int_128 type:bitmask default:0x01
246 0x01 packed_mpy 128 bit SIMD integer multiply operations
253 name:simd_int_64 type:bitmask default:0x01
254 0x01 packed_mpy SIMD integer 64 bit packed multiply operations
261 name:snoopq_requests type:bitmask default:0x01
262 0x01 data Snoop data requests
265 name:snoopq_requests_outstanding type:bitmask default:0x01
266 0x01 data Outstanding snoop data requests
269 name:snoop_response type:bitmask default:0x01
270 0x01 hit Thread responded HIT to snoop
276 name:ssex_uops_retired type:bitmask default:0x01
277 0x01 packed_single SIMD Packed-Single Uops retired (Precise Event)
285 name:uops_decoded type:bitmask default:0x01
286 0x01 stall_cycles Cycles no Uops are decoded
291 0x01 port0 Uops executed on port 0
301 name:uops_issued type:bitmask default:0x01
302 0x01 any Uops issued
304 name:uops_retired type:bitmask default:0x01
305 0x01 active_cycles Cycles Uops are being retired