Lines Matching refs:cpu_env
90 static TCGv_ptr cpu_env; variable
117 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); in arm_translate_init()
144 tcg_gen_ld_i32(tmp, cpu_env, offset); in load_cpu_offset()
152 tcg_gen_st_i32(var, cpu_env, offset); in store_cpu_offset()
378 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
392 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF)); in gen_logic_CC()
393 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF)); in gen_logic_CC()
533 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); in gen_arm_parallel_addsub()
539 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); in gen_arm_parallel_addsub()
580 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); in gen_thumb2_parallel_addsub()
586 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); in gen_thumb2_parallel_addsub()
735 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb)); in gen_bx_im()
912 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
914 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
928 gen_helper_vfp_muld(cpu_F1d, cpu_F0d, cpu_F1d, cpu_env); in VFP_OP2()
930 gen_helper_vfp_muls(cpu_F1s, cpu_F0s, cpu_F1s, cpu_env); in VFP_OP2()
963 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env); in gen_vfp_sqrt()
965 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env); in gen_vfp_sqrt()
971 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env); in gen_vfp_cmp()
973 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env); in gen_vfp_cmp()
979 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env); in gen_vfp_cmpe()
981 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env); in gen_vfp_cmpe()
1002 tcg_gen_addi_ptr(statusptr, cpu_env, offset); \
1025 tcg_gen_addi_ptr(statusptr, cpu_env, offset); \ in VFP_GEN_ITOF()
1051 tcg_gen_addi_ptr(statusptr, cpu_env, offset); \
1113 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass)); in neon_load_reg()
1119 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass)); in neon_store_reg()
1125 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); in neon_load_reg64()
1130 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); in neon_store_reg64()
1141 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg)); in gen_mov_F0_vreg()
1143 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg)); in gen_mov_F0_vreg()
1149 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg)); in gen_mov_F1_vreg()
1151 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg)); in gen_mov_F1_vreg()
1157 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg)); in gen_mov_vreg_F0()
1159 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg)); in gen_mov_vreg_F0()
1166 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg])); in iwmmxt_load_reg()
1171 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg])); in iwmmxt_store_reg()
1177 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg])); in iwmmxt_load_creg()
1183 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg])); in iwmmxt_store_creg()
2464 gen_helper_get_cp(tmp, cpu_env, tmp2); in disas_cp_insn()
2473 gen_helper_set_cp(cpu_env, tmp2, tmp); in disas_cp_insn()
2615 gen_helper_get_cp15(tmp, cpu_env, tmp2); in disas_cp15_insn()
2623 gen_helper_set_cp15(cpu_env, tmp2, tmp); in disas_cp15_insn()
2878 gen_helper_vfp_get_fpscr(tmp, cpu_env); in disas_vfp_insn()
2915 gen_helper_vfp_set_fpscr(cpu_env, tmp); in disas_vfp_insn()
3149 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env); in disas_vfp_insn()
3157 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env); in disas_vfp_insn()
3164 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); in disas_vfp_insn()
3176 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); in disas_vfp_insn()
3200 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env); in disas_vfp_insn()
3202 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env); in disas_vfp_insn()
3661 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch])); in neon_load_scratch()
3667 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch])); in neon_store_scratch()
3910 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0)); in disas_neon_ls_insn()
3911 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1)); in disas_neon_ls_insn()
3913 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 0)); in disas_neon_ls_insn()
3914 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 1)); in disas_neon_ls_insn()
3922 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0)); in disas_neon_ls_insn()
3923 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1)); in disas_neon_ls_insn()
4812 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env); in disas_neon_data_insn()
4814 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env); in disas_neon_data_insn()
5163 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass)); in disas_neon_data_insn()
5175 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass)); in disas_neon_data_insn()
5780 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0)); in disas_neon_data_insn()
5781 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); in disas_neon_data_insn()
5782 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1)); in disas_neon_data_insn()
5783 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env); in disas_neon_data_insn()
5786 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2)); in disas_neon_data_insn()
5787 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); in disas_neon_data_insn()
5788 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3)); in disas_neon_data_insn()
5791 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env); in disas_neon_data_insn()
5806 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); in disas_neon_data_insn()
5807 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0)); in disas_neon_data_insn()
5809 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); in disas_neon_data_insn()
5810 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1)); in disas_neon_data_insn()
5813 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); in disas_neon_data_insn()
5814 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2)); in disas_neon_data_insn()
5816 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); in disas_neon_data_insn()
5817 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3)); in disas_neon_data_insn()
5825 tcg_gen_ld_f32(cpu_F0s, cpu_env, in disas_neon_data_insn()
5974 gen_helper_recpe_u32(tmp, tmp, cpu_env); in disas_neon_data_insn()
5977 gen_helper_rsqrte_u32(tmp, tmp, cpu_env); in disas_neon_data_insn()
5980 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env); in disas_neon_data_insn()
5983 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env); in disas_neon_data_insn()
6004 tcg_gen_st_f32(cpu_F0s, cpu_env, in disas_neon_data_insn()
6177 gen_helper_set_teecr(cpu_env, tmp); in disas_cp14_write()
6521 gen_helper_get_r13_banked(addr, cpu_env, tmp); in disas_arm_insn()
6550 gen_helper_set_r13_banked(cpu_env, tmp, addr); in disas_arm_insn()
7322 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE)); in disas_arm_insn()
7976 gen_helper_get_r13_banked(addr, cpu_env, tmp); in disas_thumb2_insn()
7994 gen_helper_set_r13_banked(cpu_env, tmp, addr); in disas_thumb2_insn()
8193 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE)); in disas_thumb2_insn()
8428 gen_helper_v7m_msr(cpu_env, addr, tmp); in disas_thumb2_insn()
8507 gen_helper_v7m_mrs(tmp, cpu_env, addr); in disas_thumb2_insn()
9425 gen_helper_v7m_msr(cpu_env, addr, tmp); in disas_thumb_insn()
9431 gen_helper_v7m_msr(cpu_env, addr, tmp); in disas_thumb_insn()