Lines Matching refs:cpu_env
64 static TCGv_ptr cpu_env; variable
279 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET); in gen_op_mov_reg_v()
281 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET); in gen_op_mov_reg_v()
285 tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); in gen_op_mov_reg_v()
289 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); in gen_op_mov_reg_v()
292 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET); in gen_op_mov_reg_v()
296 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_mov_reg_v()
301 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); in gen_op_mov_reg_v()
321 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); in gen_op_mov_reg_A0()
325 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); in gen_op_mov_reg_A0()
328 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET); in gen_op_mov_reg_A0()
332 tcg_gen_st_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_mov_reg_A0()
337 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); in gen_op_mov_reg_A0()
350 tcg_gen_ld8u_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET); in gen_op_mov_v_reg()
355 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_mov_v_reg()
367 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); in gen_op_movl_A0_reg()
402 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip)); in gen_op_jmp_T0()
409 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_add_reg_im()
411 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); in gen_op_add_reg_im()
414 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_add_reg_im()
419 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_add_reg_im()
423 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_add_reg_im()
425 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_add_reg_im()
435 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_add_reg_T0()
437 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); in gen_op_add_reg_T0()
440 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_add_reg_T0()
445 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_add_reg_T0()
449 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_add_reg_T0()
451 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_add_reg_T0()
464 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_addl_A0_reg_sN()
475 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET); in gen_op_movl_A0_seg()
480 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base)); in gen_op_addl_A0_seg()
490 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base)); in gen_op_movq_A0_seg()
495 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base)); in gen_op_addq_A0_seg()
501 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_movq_A0_reg()
506 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); in gen_op_addq_A0_reg_sN()
605 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip)); in gen_jmp_im()
666 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df)); in gen_op_movl_T0_Dshift()
706 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX])); in gen_op_jnz_ecx()
713 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX])); in gen_op_jz_ecx()
2372 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, in gen_op_movl_T0_seg()
2379 tcg_gen_st32_tl(cpu_T[0], cpu_env, in gen_op_movl_seg_T0_vm()
2382 tcg_gen_st_tl(cpu_T[0], cpu_env, in gen_op_movl_seg_T0_vm()
2747 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset); in gen_ldq_env_A0()
2753 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset); in gen_stq_env_A0()
2761 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); in gen_ldo_env_A0()
2764 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); in gen_ldo_env_A0()
2770 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); in gen_sto_env_A0()
2773 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); in gen_sto_env_A0()
2779 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); in gen_op_movo()
2780 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); in gen_op_movo()
2781 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8); in gen_op_movo()
2782 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8); in gen_op_movo()
2787 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); in gen_op_movq()
2788 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); in gen_op_movq()
2793 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset); in gen_op_movl()
2794 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset); in gen_op_movl()
2800 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); in gen_op_movq_env_0()
3174 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); in gen_sse()
3179 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, in gen_sse()
3189 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, in gen_sse()
3196 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, in gen_sse()
3208 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, in gen_sse()
3210 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, in gen_sse()
3233 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); in gen_sse()
3235 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); in gen_sse()
3236 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); in gen_sse()
3237 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); in gen_sse()
3249 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); in gen_sse()
3250 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); in gen_sse()
3328 tcg_gen_ld_i64(cpu_T[0], cpu_env, in gen_sse()
3334 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, in gen_sse()
3342 tcg_gen_ld_i64(cpu_T[0], cpu_env, in gen_sse()
3348 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, in gen_sse()
3392 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); in gen_sse()
3437 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); in gen_sse()
3439 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))); in gen_sse()
3443 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); in gen_sse()
3445 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); in gen_sse()
3458 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); in gen_sse()
3459 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset); in gen_sse()
3464 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, in gen_sse()
3472 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, in gen_sse()
3490 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); in gen_sse()
3491 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); in gen_sse()
3507 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); in gen_sse()
3530 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); in gen_sse()
3531 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); in gen_sse()
3558 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); in gen_sse()
3567 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); in gen_sse()
3583 tcg_gen_st16_tl(cpu_T[0], cpu_env, in gen_sse()
3587 tcg_gen_st16_tl(cpu_T[0], cpu_env, in gen_sse()
3600 tcg_gen_ld16u_tl(cpu_T[0], cpu_env, in gen_sse()
3605 tcg_gen_ld16u_tl(cpu_T[0], cpu_env, in gen_sse()
3641 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); in gen_sse()
3645 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx)); in gen_sse()
3687 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset + in gen_sse()
3693 tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset + in gen_sse()
3716 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); in gen_sse()
3717 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); in gen_sse()
3776 tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, in gen_sse()
3785 tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, in gen_sse()
3795 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, in gen_sse()
3806 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, in gen_sse()
3820 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, in gen_sse()
3834 tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, in gen_sse()
3839 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, in gen_sse()
3847 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, in gen_sse()
3852 cpu_env, offsetof(CPUX86State, in gen_sse()
3856 cpu_env, offsetof(CPUX86State, in gen_sse()
3860 cpu_env, offsetof(CPUX86State, in gen_sse()
3864 cpu_env, offsetof(CPUX86State, in gen_sse()
3875 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, in gen_sse()
3885 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, in gen_sse()
3926 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); in gen_sse()
3927 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); in gen_sse()
3955 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); in gen_sse()
3986 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); in gen_sse()
3987 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); in gen_sse()
3993 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); in gen_sse()
3994 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); in gen_sse()
4003 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); in gen_sse()
4004 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); in gen_sse()
4023 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); in gen_sse()
4024 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); in gen_sse()
4028 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); in gen_sse()
4029 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); in gen_sse()
4839 tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUState, regs[R_EAX])); in disas_insn()
5414 tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_ECX])); in disas_insn()
6322 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); in disas_insn()
6325 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET); in disas_insn()
6436 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df)); in disas_insn()
6440 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df)); in disas_insn()
6919 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector)); in disas_insn()
6942 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector)); in disas_insn()
6989 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit)); in disas_insn()
6992 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)); in disas_insn()
7038 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit)); in disas_insn()
7041 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)); in disas_insn()
7146 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base)); in disas_insn()
7147 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit)); in disas_insn()
7149 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base)); in disas_insn()
7150 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit)); in disas_insn()
7157 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4); in disas_insn()
7159 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0])); in disas_insn()
7182 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,segs[R_GS].base)); in disas_insn()
7183 tcg_gen_ld_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,kernelgsbase)); in disas_insn()
7184 tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,segs[R_GS].base)); in disas_insn()
7185 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,kernelgsbase)); in disas_insn()
7403 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg])); in disas_insn()
7477 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); in disas_insn()
7479 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); in disas_insn()
7583 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); in optimize_flags_init()