Lines Matching refs:rs
371 Register rs; in GetRsReg() local
372 rs.code_ = (instr & kRsFieldMask) >> kRsShift; in GetRsReg()
373 return rs; in GetRsReg()
583 uint32_t rs = GetRs(instr); in IsNop() local
592 rs == static_cast<uint32_t>(ToNumber(zero_reg)) && in IsNop()
854 Register rs, in GenInstrRegister() argument
859 ASSERT(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa)); in GenInstrRegister()
860 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) in GenInstrRegister()
867 Register rs, in GenInstrRegister() argument
872 ASSERT(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb)); in GenInstrRegister()
873 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) in GenInstrRegister()
923 Register rs, in GenInstrImmediate() argument
926 ASSERT(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j))); in GenInstrImmediate()
927 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) in GenInstrImmediate()
934 Register rs, in GenInstrImmediate() argument
937 ASSERT(rs.is_valid() && (is_int16(j) || is_uint16(j))); in GenInstrImmediate()
938 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask); in GenInstrImmediate()
944 Register rs, in GenInstrImmediate() argument
947 ASSERT(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j))); in GenInstrImmediate()
949 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift) in GenInstrImmediate()
1070 void Assembler::beq(Register rs, Register rt, int16_t offset) { in beq() argument
1072 GenInstrImmediate(BEQ, rs, rt, offset); in beq()
1077 void Assembler::bgez(Register rs, int16_t offset) { in bgez() argument
1079 GenInstrImmediate(REGIMM, rs, BGEZ, offset); in bgez()
1084 void Assembler::bgezal(Register rs, int16_t offset) { in bgezal() argument
1087 GenInstrImmediate(REGIMM, rs, BGEZAL, offset); in bgezal()
1092 void Assembler::bgtz(Register rs, int16_t offset) { in bgtz() argument
1094 GenInstrImmediate(BGTZ, rs, zero_reg, offset); in bgtz()
1099 void Assembler::blez(Register rs, int16_t offset) { in blez() argument
1101 GenInstrImmediate(BLEZ, rs, zero_reg, offset); in blez()
1106 void Assembler::bltz(Register rs, int16_t offset) { in bltz() argument
1108 GenInstrImmediate(REGIMM, rs, BLTZ, offset); in bltz()
1113 void Assembler::bltzal(Register rs, int16_t offset) { in bltzal() argument
1116 GenInstrImmediate(REGIMM, rs, BLTZAL, offset); in bltzal()
1121 void Assembler::bne(Register rs, Register rt, int16_t offset) { in bne() argument
1123 GenInstrImmediate(BNE, rs, rt, offset); in bne()
1139 void Assembler::jr(Register rs) { in jr() argument
1141 if (rs.is(ra)) { in jr()
1144 GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR); in jr()
1161 void Assembler::jalr(Register rs, Register rd) { in jalr() argument
1164 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR); in jalr()
1169 void Assembler::j_or_jr(int32_t target, Register rs) { in j_or_jr() argument
1182 void Assembler::jal_or_jalr(int32_t target, Register rs) { in jal_or_jalr() argument
1199 void Assembler::addu(Register rd, Register rs, Register rt) { in addu() argument
1200 GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU); in addu()
1204 void Assembler::addiu(Register rd, Register rs, int32_t j) { in addiu() argument
1205 GenInstrImmediate(ADDIU, rs, rd, j); in addiu()
1209 void Assembler::subu(Register rd, Register rs, Register rt) { in subu() argument
1210 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU); in subu()
1214 void Assembler::mul(Register rd, Register rs, Register rt) { in mul() argument
1215 GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL); in mul()
1219 void Assembler::mult(Register rs, Register rt) { in mult() argument
1220 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULT); in mult()
1224 void Assembler::multu(Register rs, Register rt) { in multu() argument
1225 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU); in multu()
1229 void Assembler::div(Register rs, Register rt) { in div() argument
1230 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIV); in div()
1234 void Assembler::divu(Register rs, Register rt) { in divu() argument
1235 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU); in divu()
1241 void Assembler::and_(Register rd, Register rs, Register rt) { in and_() argument
1242 GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND); in and_()
1246 void Assembler::andi(Register rt, Register rs, int32_t j) { in andi() argument
1248 GenInstrImmediate(ANDI, rs, rt, j); in andi()
1252 void Assembler::or_(Register rd, Register rs, Register rt) { in or_() argument
1253 GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR); in or_()
1257 void Assembler::ori(Register rt, Register rs, int32_t j) { in ori() argument
1259 GenInstrImmediate(ORI, rs, rt, j); in ori()
1263 void Assembler::xor_(Register rd, Register rs, Register rt) { in xor_() argument
1264 GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR); in xor_()
1268 void Assembler::xori(Register rt, Register rs, int32_t j) { in xori() argument
1270 GenInstrImmediate(XORI, rs, rt, j); in xori()
1274 void Assembler::nor(Register rd, Register rs, Register rt) { in nor() argument
1275 GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR); in nor()
1293 void Assembler::sllv(Register rd, Register rt, Register rs) { in sllv() argument
1294 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV); in sllv()
1303 void Assembler::srlv(Register rd, Register rt, Register rs) { in srlv() argument
1304 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV); in srlv()
1313 void Assembler::srav(Register rd, Register rt, Register rs) { in srav() argument
1314 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV); in srav()
1328 void Assembler::rotrv(Register rd, Register rt, Register rs) { in rotrv() argument
1330 ASSERT(rd.is_valid() && rt.is_valid() && rs.is_valid() ); in rotrv()
1332 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) in rotrv()
1349 void Assembler::lb(Register rd, const MemOperand& rs) { in lb() argument
1350 if (is_int16(rs.offset_)) { in lb()
1351 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_); in lb()
1353 LoadRegPlusOffsetToAt(rs); in lb()
1359 void Assembler::lbu(Register rd, const MemOperand& rs) { in lbu() argument
1360 if (is_int16(rs.offset_)) { in lbu()
1361 GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_); in lbu()
1363 LoadRegPlusOffsetToAt(rs); in lbu()
1369 void Assembler::lh(Register rd, const MemOperand& rs) { in lh() argument
1370 if (is_int16(rs.offset_)) { in lh()
1371 GenInstrImmediate(LH, rs.rm(), rd, rs.offset_); in lh()
1373 LoadRegPlusOffsetToAt(rs); in lh()
1379 void Assembler::lhu(Register rd, const MemOperand& rs) { in lhu() argument
1380 if (is_int16(rs.offset_)) { in lhu()
1381 GenInstrImmediate(LHU, rs.rm(), rd, rs.offset_); in lhu()
1383 LoadRegPlusOffsetToAt(rs); in lhu()
1389 void Assembler::lw(Register rd, const MemOperand& rs) { in lw() argument
1390 if (is_int16(rs.offset_)) { in lw()
1391 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_); in lw()
1393 LoadRegPlusOffsetToAt(rs); in lw()
1399 void Assembler::lwl(Register rd, const MemOperand& rs) { in lwl() argument
1400 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_); in lwl()
1404 void Assembler::lwr(Register rd, const MemOperand& rs) { in lwr() argument
1405 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_); in lwr()
1409 void Assembler::sb(Register rd, const MemOperand& rs) { in sb() argument
1410 if (is_int16(rs.offset_)) { in sb()
1411 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_); in sb()
1413 LoadRegPlusOffsetToAt(rs); in sb()
1419 void Assembler::sh(Register rd, const MemOperand& rs) { in sh() argument
1420 if (is_int16(rs.offset_)) { in sh()
1421 GenInstrImmediate(SH, rs.rm(), rd, rs.offset_); in sh()
1423 LoadRegPlusOffsetToAt(rs); in sh()
1429 void Assembler::sw(Register rd, const MemOperand& rs) { in sw() argument
1430 if (is_int16(rs.offset_)) { in sw()
1431 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_); in sw()
1433 LoadRegPlusOffsetToAt(rs); in sw()
1439 void Assembler::swl(Register rd, const MemOperand& rs) { in swl() argument
1440 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_); in swl()
1444 void Assembler::swr(Register rd, const MemOperand& rs) { in swr() argument
1445 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_); in swr()
1489 void Assembler::tge(Register rs, Register rt, uint16_t code) { in tge() argument
1491 Instr instr = SPECIAL | TGE | rs.code() << kRsShift in tge()
1497 void Assembler::tgeu(Register rs, Register rt, uint16_t code) { in tgeu() argument
1499 Instr instr = SPECIAL | TGEU | rs.code() << kRsShift in tgeu()
1505 void Assembler::tlt(Register rs, Register rt, uint16_t code) { in tlt() argument
1508 SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; in tlt()
1513 void Assembler::tltu(Register rs, Register rt, uint16_t code) { in tltu() argument
1516 SPECIAL | TLTU | rs.code() << kRsShift in tltu()
1522 void Assembler::teq(Register rs, Register rt, uint16_t code) { in teq() argument
1525 SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; in teq()
1530 void Assembler::tne(Register rs, Register rt, uint16_t code) { in tne() argument
1533 SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; in tne()
1551 void Assembler::slt(Register rd, Register rs, Register rt) { in slt() argument
1552 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT); in slt()
1556 void Assembler::sltu(Register rd, Register rs, Register rt) { in sltu() argument
1557 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU); in sltu()
1561 void Assembler::slti(Register rt, Register rs, int32_t j) { in slti() argument
1562 GenInstrImmediate(SLTI, rs, rt, j); in slti()
1566 void Assembler::sltiu(Register rt, Register rs, int32_t j) { in sltiu() argument
1567 GenInstrImmediate(SLTIU, rs, rt, j); in sltiu()
1572 void Assembler::movz(Register rd, Register rs, Register rt) { in movz() argument
1573 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ); in movz()
1577 void Assembler::movn(Register rd, Register rs, Register rt) { in movn() argument
1578 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN); in movn()
1582 void Assembler::movt(Register rd, Register rs, uint16_t cc) { in movt() argument
1585 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); in movt()
1589 void Assembler::movf(Register rd, Register rs, uint16_t cc) { in movf() argument
1592 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); in movf()
1597 void Assembler::clz(Register rd, Register rs) { in clz() argument
1599 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ); in clz()
1603 void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) { in ins_() argument
1607 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS); in ins_()
1611 void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) { in ext_() argument
1615 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT); in ext_()