Lines Matching refs:rs
543 void MacroAssembler::Addu(Register rd, Register rs, const Operand& rt) { in Addu() argument
545 addu(rd, rs, rt.rm()); in Addu()
548 addiu(rd, rs, rt.imm32_); in Addu()
551 ASSERT(!rs.is(at)); in Addu()
553 addu(rd, rs, at); in Addu()
559 void MacroAssembler::Subu(Register rd, Register rs, const Operand& rt) { in Subu() argument
561 subu(rd, rs, rt.rm()); in Subu()
564 addiu(rd, rs, -rt.imm32_); // No subiu instr, use addiu(x, y, -imm). in Subu()
567 ASSERT(!rs.is(at)); in Subu()
569 subu(rd, rs, at); in Subu()
575 void MacroAssembler::Mul(Register rd, Register rs, const Operand& rt) { in Mul() argument
578 mult(rs, rt.rm()); in Mul()
581 mul(rd, rs, rt.rm()); in Mul()
585 ASSERT(!rs.is(at)); in Mul()
588 mult(rs, at); in Mul()
591 mul(rd, rs, at); in Mul()
597 void MacroAssembler::Mult(Register rs, const Operand& rt) { in Mult() argument
599 mult(rs, rt.rm()); in Mult()
602 ASSERT(!rs.is(at)); in Mult()
604 mult(rs, at); in Mult()
609 void MacroAssembler::Multu(Register rs, const Operand& rt) { in Multu() argument
611 multu(rs, rt.rm()); in Multu()
614 ASSERT(!rs.is(at)); in Multu()
616 multu(rs, at); in Multu()
621 void MacroAssembler::Div(Register rs, const Operand& rt) { in Div() argument
623 div(rs, rt.rm()); in Div()
626 ASSERT(!rs.is(at)); in Div()
628 div(rs, at); in Div()
633 void MacroAssembler::Divu(Register rs, const Operand& rt) { in Divu() argument
635 divu(rs, rt.rm()); in Divu()
638 ASSERT(!rs.is(at)); in Divu()
640 divu(rs, at); in Divu()
645 void MacroAssembler::And(Register rd, Register rs, const Operand& rt) { in And() argument
647 and_(rd, rs, rt.rm()); in And()
650 andi(rd, rs, rt.imm32_); in And()
653 ASSERT(!rs.is(at)); in And()
655 and_(rd, rs, at); in And()
661 void MacroAssembler::Or(Register rd, Register rs, const Operand& rt) { in Or() argument
663 or_(rd, rs, rt.rm()); in Or()
666 ori(rd, rs, rt.imm32_); in Or()
669 ASSERT(!rs.is(at)); in Or()
671 or_(rd, rs, at); in Or()
677 void MacroAssembler::Xor(Register rd, Register rs, const Operand& rt) { in Xor() argument
679 xor_(rd, rs, rt.rm()); in Xor()
682 xori(rd, rs, rt.imm32_); in Xor()
685 ASSERT(!rs.is(at)); in Xor()
687 xor_(rd, rs, at); in Xor()
693 void MacroAssembler::Nor(Register rd, Register rs, const Operand& rt) { in Nor() argument
695 nor(rd, rs, rt.rm()); in Nor()
698 ASSERT(!rs.is(at)); in Nor()
700 nor(rd, rs, at); in Nor()
705 void MacroAssembler::Neg(Register rs, const Operand& rt) { in Neg() argument
707 ASSERT(!at.is(rs)); in Neg()
710 xor_(rs, rt.rm(), at); in Neg()
714 void MacroAssembler::Slt(Register rd, Register rs, const Operand& rt) { in Slt() argument
716 slt(rd, rs, rt.rm()); in Slt()
719 slti(rd, rs, rt.imm32_); in Slt()
722 ASSERT(!rs.is(at)); in Slt()
724 slt(rd, rs, at); in Slt()
730 void MacroAssembler::Sltu(Register rd, Register rs, const Operand& rt) { in Sltu() argument
732 sltu(rd, rs, rt.rm()); in Sltu()
735 sltiu(rd, rs, rt.imm32_); in Sltu()
738 ASSERT(!rs.is(at)); in Sltu()
740 sltu(rd, rs, at); in Sltu()
746 void MacroAssembler::Ror(Register rd, Register rs, const Operand& rt) { in Ror() argument
749 rotrv(rd, rs, rt.rm()); in Ror()
751 rotr(rd, rs, rt.imm32_); in Ror()
756 sllv(at, rs, at); in Ror()
757 srlv(rd, rs, rt.rm()); in Ror()
761 srl(rd, rs, 0); in Ror()
763 srl(at, rs, rt.imm32_); in Ror()
764 sll(rd, rs, (0x20 - rt.imm32_) & 0x1f); in Ror()
928 Register rs, in Ext() argument
935 ext_(rt, rs, pos, size); in Ext()
940 sll(rt, rs, shift_left); // Acts as a move if shift_left == 0. in Ext()
951 Register rs, in Ins() argument
959 ins_(rt, rs, pos, size); in Ins()
961 ASSERT(!rt.is(t8) && !rs.is(t8)); in Ins()
964 and_(t8, rs, at); in Ins()
984 Register rs, in Cvt_d_uw() argument
991 ASSERT(!rs.is(t9)); in Cvt_d_uw()
992 ASSERT(!rs.is(at)); in Cvt_d_uw()
995 Ext(t9, rs, 31, 1); in Cvt_d_uw()
997 Ext(at, rs, 0, 31); in Cvt_d_uw()
1072 Register rs, in Trunc_uw_d() argument
1075 ASSERT(!rs.is(at)); in Trunc_uw_d()
1090 mfc1(rs, scratch); in Trunc_uw_d()
1091 Or(rs, rs, 1 << 31); in Trunc_uw_d()
1098 mfc1(rs, scratch); in Trunc_uw_d()
1200 void MacroAssembler::Movz(Register rd, Register rs, Register rt) { in Movz() argument
1204 mov(rd, rs); in Movz()
1207 movz(rd, rs, rt); in Movz()
1212 void MacroAssembler::Movn(Register rd, Register rs, Register rt) { in Movn() argument
1216 mov(rd, rs); in Movn()
1219 movn(rd, rs, rt); in Movn()
1224 void MacroAssembler::Movt(Register rd, Register rs, uint16_t cc) { in Movt() argument
1229 ASSERT(!(rs.is(t8) || rd.is(t8))); in Movt()
1242 mov(rd, rs); in Movt()
1245 movt(rd, rs, cc); in Movt()
1250 void MacroAssembler::Movf(Register rd, Register rs, uint16_t cc) { in Movf() argument
1255 ASSERT(!(rs.is(t8) || rd.is(t8))); in Movf()
1268 mov(rd, rs); in Movf()
1271 movf(rd, rs, cc); in Movf()
1276 void MacroAssembler::Clz(Register rd, Register rs) { in Clz() argument
1278 ASSERT(!(rd.is(t8) || rd.is(t9)) && !(rs.is(t8) || rs.is(t9))); in Clz()
1282 mov(at, rs); in Clz()
1293 clz(rd, rs); in Clz()
1588 #define BRANCH_ARGS_CHECK(cond, rs, rt) ASSERT( \ argument
1589 (cond == cc_always && rs.is(zero_reg) && rt.rm().is(zero_reg)) || \
1590 (cond != cc_always && (!rs.is(zero_reg) || !rt.rm().is(zero_reg))))
1598 void MacroAssembler::Branch(int16_t offset, Condition cond, Register rs, in Branch() argument
1601 BranchShort(offset, cond, rs, rt, bdslot); in Branch()
1622 void MacroAssembler::Branch(Label* L, Condition cond, Register rs, in Branch() argument
1627 BranchShort(L, cond, rs, rt, bdslot); in Branch()
1631 BranchShort(&skip, neg_cond, rs, rt); in Branch()
1639 BranchShort(&skip, neg_cond, rs, rt); in Branch()
1643 BranchShort(L, cond, rs, rt, bdslot); in Branch()
1651 Register rs, in Branch() argument
1655 Branch(L, cond, rs, Operand(at), bdslot); in Branch()
1668 void MacroAssembler::BranchShort(int16_t offset, Condition cond, Register rs, in BranchShort() argument
1671 BRANCH_ARGS_CHECK(cond, rs, rt); in BranchShort()
1672 ASSERT(!rs.is(zero_reg)); in BranchShort()
1685 beq(rs, r2, offset); in BranchShort()
1688 bne(rs, r2, offset); in BranchShort()
1693 bgtz(rs, offset); in BranchShort()
1695 slt(scratch, r2, rs); in BranchShort()
1701 bgez(rs, offset); in BranchShort()
1703 slt(scratch, rs, r2); in BranchShort()
1709 bltz(rs, offset); in BranchShort()
1711 slt(scratch, rs, r2); in BranchShort()
1717 blez(rs, offset); in BranchShort()
1719 slt(scratch, r2, rs); in BranchShort()
1726 bgtz(rs, offset); in BranchShort()
1728 sltu(scratch, r2, rs); in BranchShort()
1734 bgez(rs, offset); in BranchShort()
1736 sltu(scratch, rs, r2); in BranchShort()
1745 sltu(scratch, rs, r2); in BranchShort()
1753 sltu(scratch, r2, rs); in BranchShort()
1770 ASSERT(!scratch.is(rs)); in BranchShort()
1773 beq(rs, r2, offset); in BranchShort()
1777 ASSERT(!scratch.is(rs)); in BranchShort()
1780 bne(rs, r2, offset); in BranchShort()
1785 bgtz(rs, offset); in BranchShort()
1789 slt(scratch, r2, rs); in BranchShort()
1795 bgez(rs, offset); in BranchShort()
1797 slti(scratch, rs, rt.imm32_); in BranchShort()
1802 slt(scratch, rs, r2); in BranchShort()
1808 bltz(rs, offset); in BranchShort()
1810 slti(scratch, rs, rt.imm32_); in BranchShort()
1815 slt(scratch, rs, r2); in BranchShort()
1821 blez(rs, offset); in BranchShort()
1825 slt(scratch, r2, rs); in BranchShort()
1832 bgtz(rs, offset); in BranchShort()
1836 sltu(scratch, r2, rs); in BranchShort()
1842 bgez(rs, offset); in BranchShort()
1844 sltiu(scratch, rs, rt.imm32_); in BranchShort()
1849 sltu(scratch, rs, r2); in BranchShort()
1858 sltiu(scratch, rs, rt.imm32_); in BranchShort()
1863 sltu(scratch, rs, r2); in BranchShort()
1873 sltu(scratch, r2, rs); in BranchShort()
1899 void MacroAssembler::BranchShort(Label* L, Condition cond, Register rs, in BranchShort() argument
1902 BRANCH_ARGS_CHECK(cond, rs, rt); in BranchShort()
1919 beq(rs, r2, offset); in BranchShort()
1923 bne(rs, r2, offset); in BranchShort()
1929 bgtz(rs, offset); in BranchShort()
1931 slt(scratch, r2, rs); in BranchShort()
1939 bgez(rs, offset); in BranchShort()
1941 slt(scratch, rs, r2); in BranchShort()
1949 bltz(rs, offset); in BranchShort()
1951 slt(scratch, rs, r2); in BranchShort()
1959 blez(rs, offset); in BranchShort()
1961 slt(scratch, r2, rs); in BranchShort()
1970 bgtz(rs, offset); in BranchShort()
1972 sltu(scratch, r2, rs); in BranchShort()
1980 bgez(rs, offset); in BranchShort()
1982 sltu(scratch, rs, r2); in BranchShort()
1992 sltu(scratch, rs, r2); in BranchShort()
2002 sltu(scratch, r2, rs); in BranchShort()
2020 ASSERT(!scratch.is(rs)); in BranchShort()
2024 beq(rs, r2, offset); in BranchShort()
2027 ASSERT(!scratch.is(rs)); in BranchShort()
2031 bne(rs, r2, offset); in BranchShort()
2037 bgtz(rs, offset); in BranchShort()
2039 ASSERT(!scratch.is(rs)); in BranchShort()
2042 slt(scratch, r2, rs); in BranchShort()
2050 bgez(rs, offset); in BranchShort()
2052 slti(scratch, rs, rt.imm32_); in BranchShort()
2056 ASSERT(!scratch.is(rs)); in BranchShort()
2059 slt(scratch, rs, r2); in BranchShort()
2067 bltz(rs, offset); in BranchShort()
2069 slti(scratch, rs, rt.imm32_); in BranchShort()
2073 ASSERT(!scratch.is(rs)); in BranchShort()
2076 slt(scratch, rs, r2); in BranchShort()
2084 blez(rs, offset); in BranchShort()
2086 ASSERT(!scratch.is(rs)); in BranchShort()
2089 slt(scratch, r2, rs); in BranchShort()
2098 bgtz(rs, offset); in BranchShort()
2100 ASSERT(!scratch.is(rs)); in BranchShort()
2103 sltu(scratch, r2, rs); in BranchShort()
2111 bgez(rs, offset); in BranchShort()
2113 sltiu(scratch, rs, rt.imm32_); in BranchShort()
2117 ASSERT(!scratch.is(rs)); in BranchShort()
2120 sltu(scratch, rs, r2); in BranchShort()
2130 sltiu(scratch, rs, rt.imm32_); in BranchShort()
2134 ASSERT(!scratch.is(rs)); in BranchShort()
2137 sltu(scratch, rs, r2); in BranchShort()
2147 ASSERT(!scratch.is(rs)); in BranchShort()
2150 sltu(scratch, r2, rs); in BranchShort()
2172 void MacroAssembler::BranchAndLink(int16_t offset, Condition cond, Register rs, in BranchAndLink() argument
2175 BranchAndLinkShort(offset, cond, rs, rt, bdslot); in BranchAndLink()
2196 void MacroAssembler::BranchAndLink(Label* L, Condition cond, Register rs, in BranchAndLink() argument
2201 BranchAndLinkShort(L, cond, rs, rt, bdslot); in BranchAndLink()
2205 BranchShort(&skip, neg_cond, rs, rt); in BranchAndLink()
2213 BranchShort(&skip, neg_cond, rs, rt); in BranchAndLink()
2217 BranchAndLinkShort(L, cond, rs, rt, bdslot); in BranchAndLink()
2237 Register rs, const Operand& rt, in BranchAndLinkShort() argument
2239 BRANCH_ARGS_CHECK(cond, rs, rt); in BranchAndLinkShort()
2255 bne(rs, r2, 2); in BranchAndLinkShort()
2260 beq(rs, r2, 2); in BranchAndLinkShort()
2267 slt(scratch, r2, rs); in BranchAndLinkShort()
2272 slt(scratch, rs, r2); in BranchAndLinkShort()
2277 slt(scratch, rs, r2); in BranchAndLinkShort()
2282 slt(scratch, r2, rs); in BranchAndLinkShort()
2289 sltu(scratch, r2, rs); in BranchAndLinkShort()
2294 sltu(scratch, rs, r2); in BranchAndLinkShort()
2299 sltu(scratch, rs, r2); in BranchAndLinkShort()
2304 sltu(scratch, r2, rs); in BranchAndLinkShort()
2327 void MacroAssembler::BranchAndLinkShort(Label* L, Condition cond, Register rs, in BranchAndLinkShort() argument
2330 BRANCH_ARGS_CHECK(cond, rs, rt); in BranchAndLinkShort()
2348 bne(rs, r2, 2); in BranchAndLinkShort()
2354 beq(rs, r2, 2); in BranchAndLinkShort()
2362 slt(scratch, r2, rs); in BranchAndLinkShort()
2368 slt(scratch, rs, r2); in BranchAndLinkShort()
2374 slt(scratch, rs, r2); in BranchAndLinkShort()
2380 slt(scratch, r2, rs); in BranchAndLinkShort()
2388 sltu(scratch, r2, rs); in BranchAndLinkShort()
2394 sltu(scratch, rs, r2); in BranchAndLinkShort()
2400 sltu(scratch, rs, r2); in BranchAndLinkShort()
2406 sltu(scratch, r2, rs); in BranchAndLinkShort()
2427 Register rs, in Jump() argument
2434 BRANCH_ARGS_CHECK(cond, rs, rt); in Jump()
2435 Branch(2, NegateCondition(cond), rs, rt); in Jump()
2447 Register rs, in Jump() argument
2452 Branch(USE_DELAY_SLOT, &skip, NegateCondition(cond), rs, rt); in Jump()
2465 Register rs, in Jump() argument
2469 Jump(reinterpret_cast<intptr_t>(target), rmode, cond, rs, rt, bd); in Jump()
2476 Register rs, in Jump() argument
2480 Jump(reinterpret_cast<intptr_t>(code.location()), rmode, cond, rs, rt, bd); in Jump()
2486 Register rs, in CallSize() argument
2507 Register rs, in Call() argument
2516 BRANCH_ARGS_CHECK(cond, rs, rt); in Call()
2517 Branch(2, NegateCondition(cond), rs, rt); in Call()
2524 ASSERT_EQ(CallSize(target, cond, rs, rt, bd), in Call()
2532 Register rs, in CallSize() argument
2535 int size = CallSize(t9, cond, rs, rt, bd); in CallSize()
2543 Register rs, in Call() argument
2554 Call(t9, cond, rs, rt, bd); in Call()
2555 ASSERT_EQ(CallSize(target, rmode, cond, rs, rt, bd), in Call()
2564 Register rs, in CallSize() argument
2568 rmode, cond, rs, rt, bd); in CallSize()
2576 Register rs, in Call() argument
2587 Call(reinterpret_cast<Address>(code.location()), rmode, cond, rs, rt, bd); in Call()
2588 ASSERT_EQ(CallSize(code, rmode, ast_id, cond, rs, rt, bd), in Call()
2594 Register rs, in Ret() argument
2597 Jump(ra, cond, rs, rt, bd); in Ret()
4327 Register rs, Operand rt) { in Assert() argument
4329 Check(cc, msg, rs, rt); in Assert()
4362 Register rs, Operand rt) { in Check() argument
4364 Branch(&L, cc, rs, rt); in Check()