98   LOperand* destination = moves_[index].destination();  in PerformMove()  local
107     if (other_move.Blocks(destination) && !other_move.IsPending()) {  in PerformMove()
123   moves_[index].set_destination(destination);  in PerformMove()
127   if (moves_[index].source()->Equals(destination)) {  in PerformMove()
137     if (other_move.Blocks(destination)) {  in PerformMove()
153     LOperand* destination = moves_[i].destination();  in Verify()  local
155       SLOW_ASSERT(!destination->Equals(moves_[j].destination()));  in Verify()
167   LOperand* destination = moves_[index].destination();  in EmitMove()  local
173     if (destination->IsRegister()) {  in EmitMove()
174       Register dst = cgen_->ToRegister(destination);  in EmitMove()
177       ASSERT(destination->IsStackSlot());  in EmitMove()
178       Operand dst = cgen_->ToOperand(destination);  in EmitMove()
184     if (destination->IsRegister()) {  in EmitMove()
185       Register dst = cgen_->ToRegister(destination);  in EmitMove()
188       ASSERT(destination->IsStackSlot());  in EmitMove()
189       Operand dst = cgen_->ToOperand(destination);  in EmitMove()
196     if (destination->IsRegister()) {  in EmitMove()
197       Register dst = cgen_->ToRegister(destination);  in EmitMove()
204       ASSERT(destination->IsStackSlot());  in EmitMove()
205       Operand dst = cgen_->ToOperand(destination);  in EmitMove()
218     if (destination->IsDoubleRegister()) {  in EmitMove()
219       __ movaps(cgen_->ToDoubleRegister(destination), src);  in EmitMove()
221       ASSERT(destination->IsDoubleStackSlot());  in EmitMove()
222       __ movsd(cgen_->ToOperand(destination), src);  in EmitMove()
226     if (destination->IsDoubleRegister()) {  in EmitMove()
227       __ movsd(cgen_->ToDoubleRegister(destination), src);  in EmitMove()
229       ASSERT(destination->IsDoubleStackSlot());  in EmitMove()
231       __ movsd(cgen_->ToOperand(destination), xmm0);  in EmitMove()
243   LOperand* destination = moves_[index].destination();  in EmitSwap()  local
247   if (source->IsRegister() && destination->IsRegister()) {  in EmitSwap()
250     Register dst = cgen_->ToRegister(destination);  in EmitSwap()
253   } else if ((source->IsRegister() && destination->IsStackSlot()) ||  in EmitSwap()
254              (source->IsStackSlot() && destination->IsRegister())) {  in EmitSwap()
257         cgen_->ToRegister(source->IsRegister() ? source : destination);  in EmitSwap()
259         cgen_->ToOperand(source->IsRegister() ? destination : source);  in EmitSwap()
264   } else if ((source->IsStackSlot() && destination->IsStackSlot()) ||  in EmitSwap()
265       (source->IsDoubleStackSlot() && destination->IsDoubleStackSlot())) {  in EmitSwap()
268     Operand dst = cgen_->ToOperand(destination);  in EmitSwap()
274   } else if (source->IsDoubleRegister() && destination->IsDoubleRegister()) {  in EmitSwap()
277     XMMRegister destination_reg = cgen_->ToDoubleRegister(destination);  in EmitSwap()
282   } else if (source->IsDoubleRegister() || destination->IsDoubleRegister()) {  in EmitSwap()
284     ASSERT((source->IsDoubleRegister() && destination->IsDoubleStackSlot()) ||  in EmitSwap()
285            (source->IsDoubleStackSlot() && destination->IsDoubleRegister()));  in EmitSwap()
288                                                   : destination);  in EmitSwap()
289     LOperand* other = source->IsDoubleRegister() ? destination : source;  in EmitSwap()
311       moves_[i].set_source(destination);  in EmitSwap()
312     } else if (other_move.Blocks(destination)) {  in EmitSwap()