Lines Matching refs:I1_Read
145 simcall_type I1_Read; member
1056 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size); in log_1I0D()
1081 Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size); in log_2I0D()
1083 Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size); in log_2I0D()
1114 Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size); in log_3I0D()
1116 Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size); in log_3I0D()
1118 Ir3Res = (*simulator.I1_Read)(CLG_(bb_base) + ii3->instr_offset, ii3->instr_size); in log_3I0D()
1153 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size); in log_1I1Dr()
1213 IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size); in log_1I1Dw()
1351 simulator.I1_Read = cacheuse_I1_doRead; in cachesim_post_clo_init()
1361 simulator.I1_Read = prefetch_I1_Read; in cachesim_post_clo_init()
1366 simulator.I1_Read = prefetch_I1_ref; in cachesim_post_clo_init()
1375 simulator.I1_Read = cachesim_I1_Read; in cachesim_post_clo_init()
1380 simulator.I1_Read = cachesim_I1_ref; in cachesim_post_clo_init()