| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 165 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
180 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
195 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
305 unsigned BaseReg = Base.getReg(); in EmitMemModRMByte() local
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| /external/llvm/include/llvm/Transforms/Utils/ |
| D | AddrModeMatcher.h | 37 Value *BaseReg; member
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 138 const MCOperand &BaseReg = MI->getOperand(Op); in printMemReference() local
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| D | X86IntelInstPrinter.cpp | 129 const MCOperand &BaseReg = MI->getOperand(Op); in printMemReference() local
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb1RegisterInfo.cpp | 92 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmInReg()
169 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmediate()
531 unsigned BaseReg, int64_t Offset) const { in resolveFrameIndex()
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| D | Thumb2SizeReduction.cpp | 379 unsigned BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
401 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
415 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
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| D | ARMBaseRegisterInfo.cpp | 922 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister()
946 unsigned BaseReg, int64_t Offset) const { in resolveFrameIndex()
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| D | ARMLoadStoreOptimizer.cpp | 1079 unsigned BaseReg, bool BaseKill, bool BaseUndef, in InsertLDR_STR()
1105 unsigned BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp() local
1567 unsigned &OddReg, unsigned &BaseReg, in CanFormLdStDWord()
1729 unsigned BaseReg = 0, PredReg = 0; in RescheduleOps() local
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| D | Thumb2InstrInfo.cpp | 179 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate()
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| D | ARMBaseInstrInfo.cpp | 154 unsigned BaseReg = Base.getReg(); in convertToThreeAddress() local
1579 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitARMRegPlusImmediate()
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| D | ARMISelDAGToDAG.cpp | 392 SDValue &BaseReg, in SelectImmShifterOperand()
415 SDValue &BaseReg, in SelectRegShifterOperand()
1155 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg, in SelectT2ShifterOperandReg()
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| D | ARMConstantIslandPass.cpp | 1902 unsigned BaseReg = MI->getOperand(0).getReg(); in optimizeThumb2JumpTables() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsMCInstLower.cpp | 149 MCOperand SPReg = MCOperand::CreateReg(Mips::SP), BaseReg = SPReg; in LowerCPRESTORE() local
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 637 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister()
646 unsigned BaseReg, int64_t Offset) const { in resolveFrameIndex()
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| /external/llvm/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 290 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
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| /external/llvm/lib/Transforms/Utils/ |
| D | AddrModeMatcher.cpp | 516 Value *BaseReg = AMAfter.BaseReg, *ScaledReg = AMAfter.ScaledReg; in IsProfitableToFoldIntoAddressingMode() local
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 176 unsigned BaseReg; member
604 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; in ParseIntelBracExpression() local
840 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; in ParseMemOperand() local
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| /external/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 306 const MachineOperand &BaseReg = MI->getOperand(Op); in printLeaMemReference() local
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| D | X86CodeEmitter.cpp | 471 unsigned BaseReg = Base.getReg(); in emitMemModRMByte() local
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| D | X86InstrInfo.cpp | 1314 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { in regIsPICBase()
1364 unsigned BaseReg = MI->getOperand(1).getReg(); in isReallyTriviallyReMaterializable() local
1394 unsigned BaseReg = MI->getOperand(1).getReg(); in isReallyTriviallyReMaterializable() local
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| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 906 const SCEV *BaseReg = *I; in RateFormula() local
3024 const SCEV *BaseReg = Base.BaseRegs[i]; in GenerateReassociations() local
3107 const SCEV *BaseReg = *I; in GenerateCombinations() local
3513 const SCEV *BaseReg = F.BaseRegs[N]; in GenerateCrossUseConstantOffsets() local
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 171 unsigned BaseReg = MI->getOperand(0).getReg(); in printInst() local
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