1 #if !defined (__MIPS_CPU_H__)
2 #define __MIPS_CPU_H__
3
4 #define TARGET_HAS_ICE 1
5
6 #define ELF_MACHINE EM_MIPS
7
8 #define CPUState struct CPUMIPSState
9
10 #include "config.h"
11 #include "mips-defs.h"
12 #include "cpu-defs.h"
13 #include "softfloat.h"
14
15 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
16 // XXX: move that elsewhere
17 #if defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10
18 typedef unsigned char uint_fast8_t;
19 typedef unsigned int uint_fast16_t;
20 #endif
21
22 struct CPUMIPSState;
23
24 typedef struct r4k_tlb_t r4k_tlb_t;
25 struct r4k_tlb_t {
26 target_ulong VPN;
27 uint32_t PageMask;
28 uint_fast8_t ASID;
29 uint_fast16_t G:1;
30 uint_fast16_t C0:3;
31 uint_fast16_t C1:3;
32 uint_fast16_t V0:1;
33 uint_fast16_t V1:1;
34 uint_fast16_t D0:1;
35 uint_fast16_t D1:1;
36 target_ulong PFN[2];
37 };
38
39 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
40 struct CPUMIPSTLBContext {
41 uint32_t nb_tlb;
42 uint32_t tlb_in_use;
43 int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type);
44 void (*helper_tlbwi) (void);
45 void (*helper_tlbwr) (void);
46 void (*helper_tlbp) (void);
47 void (*helper_tlbr) (void);
48 union {
49 struct {
50 r4k_tlb_t tlb[MIPS_TLB_MAX];
51 } r4k;
52 } mmu;
53 };
54
55 typedef union fpr_t fpr_t;
56 union fpr_t {
57 float64 fd; /* ieee double precision */
58 float32 fs[2];/* ieee single precision */
59 uint64_t d; /* binary double fixed-point */
60 uint32_t w[2]; /* binary single fixed-point */
61 };
62 /* define FP_ENDIAN_IDX to access the same location
63 * in the fpr_t union regardless of the host endianess
64 */
65 #if defined(HOST_WORDS_BIGENDIAN)
66 # define FP_ENDIAN_IDX 1
67 #else
68 # define FP_ENDIAN_IDX 0
69 #endif
70
71 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
72 struct CPUMIPSFPUContext {
73 /* Floating point registers */
74 fpr_t fpr[32];
75 float_status fp_status;
76 /* fpu implementation/revision register (fir) */
77 uint32_t fcr0;
78 #define FCR0_F64 22
79 #define FCR0_L 21
80 #define FCR0_W 20
81 #define FCR0_3D 19
82 #define FCR0_PS 18
83 #define FCR0_D 17
84 #define FCR0_S 16
85 #define FCR0_PRID 8
86 #define FCR0_REV 0
87 /* fcsr */
88 uint32_t fcr31;
89 #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
90 #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
91 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
92 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
93 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
94 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
95 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
96 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
97 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
98 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
99 #define FP_INEXACT 1
100 #define FP_UNDERFLOW 2
101 #define FP_OVERFLOW 4
102 #define FP_DIV0 8
103 #define FP_INVALID 16
104 #define FP_UNIMPLEMENTED 32
105 };
106
107 #define NB_MMU_MODES 3
108
109 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
110 struct CPUMIPSMVPContext {
111 int32_t CP0_MVPControl;
112 #define CP0MVPCo_CPA 3
113 #define CP0MVPCo_STLB 2
114 #define CP0MVPCo_VPC 1
115 #define CP0MVPCo_EVP 0
116 int32_t CP0_MVPConf0;
117 #define CP0MVPC0_M 31
118 #define CP0MVPC0_TLBS 29
119 #define CP0MVPC0_GS 28
120 #define CP0MVPC0_PCP 27
121 #define CP0MVPC0_PTLBE 16
122 #define CP0MVPC0_TCA 15
123 #define CP0MVPC0_PVPE 10
124 #define CP0MVPC0_PTC 0
125 int32_t CP0_MVPConf1;
126 #define CP0MVPC1_CIM 31
127 #define CP0MVPC1_CIF 30
128 #define CP0MVPC1_PCX 20
129 #define CP0MVPC1_PCP2 10
130 #define CP0MVPC1_PCP1 0
131 };
132
133 typedef struct mips_def_t mips_def_t;
134
135 #define MIPS_SHADOW_SET_MAX 16
136 #define MIPS_TC_MAX 5
137 #define MIPS_FPU_MAX 1
138 #define MIPS_DSP_ACC 4
139
140 typedef struct TCState TCState;
141 struct TCState {
142 target_ulong gpr[32];
143 target_ulong PC;
144 target_ulong HI[MIPS_DSP_ACC];
145 target_ulong LO[MIPS_DSP_ACC];
146 target_ulong ACX[MIPS_DSP_ACC];
147 target_ulong DSPControl;
148 int32_t CP0_TCStatus;
149 #define CP0TCSt_TCU3 31
150 #define CP0TCSt_TCU2 30
151 #define CP0TCSt_TCU1 29
152 #define CP0TCSt_TCU0 28
153 #define CP0TCSt_TMX 27
154 #define CP0TCSt_RNST 23
155 #define CP0TCSt_TDS 21
156 #define CP0TCSt_DT 20
157 #define CP0TCSt_DA 15
158 #define CP0TCSt_A 13
159 #define CP0TCSt_TKSU 11
160 #define CP0TCSt_IXMT 10
161 #define CP0TCSt_TASID 0
162 int32_t CP0_TCBind;
163 #define CP0TCBd_CurTC 21
164 #define CP0TCBd_TBE 17
165 #define CP0TCBd_CurVPE 0
166 target_ulong CP0_TCHalt;
167 target_ulong CP0_TCContext;
168 target_ulong CP0_TCSchedule;
169 target_ulong CP0_TCScheFBack;
170 int32_t CP0_Debug_tcstatus;
171 };
172
173 typedef struct CPUMIPSState CPUMIPSState;
174 struct CPUMIPSState {
175 TCState active_tc;
176 CPUMIPSFPUContext active_fpu;
177
178 uint32_t current_tc;
179 uint32_t current_fpu;
180
181 uint32_t SEGBITS;
182 uint32_t PABITS;
183 target_ulong SEGMask;
184 target_ulong PAMask;
185
186 int32_t CP0_Index;
187 /* CP0_MVP* are per MVP registers. */
188 int32_t CP0_Random;
189 int32_t CP0_VPEControl;
190 #define CP0VPECo_YSI 21
191 #define CP0VPECo_GSI 20
192 #define CP0VPECo_EXCPT 16
193 #define CP0VPECo_TE 15
194 #define CP0VPECo_TargTC 0
195 int32_t CP0_VPEConf0;
196 #define CP0VPEC0_M 31
197 #define CP0VPEC0_XTC 21
198 #define CP0VPEC0_TCS 19
199 #define CP0VPEC0_SCS 18
200 #define CP0VPEC0_DSC 17
201 #define CP0VPEC0_ICS 16
202 #define CP0VPEC0_MVP 1
203 #define CP0VPEC0_VPA 0
204 int32_t CP0_VPEConf1;
205 #define CP0VPEC1_NCX 20
206 #define CP0VPEC1_NCP2 10
207 #define CP0VPEC1_NCP1 0
208 target_ulong CP0_YQMask;
209 target_ulong CP0_VPESchedule;
210 target_ulong CP0_VPEScheFBack;
211 int32_t CP0_VPEOpt;
212 #define CP0VPEOpt_IWX7 15
213 #define CP0VPEOpt_IWX6 14
214 #define CP0VPEOpt_IWX5 13
215 #define CP0VPEOpt_IWX4 12
216 #define CP0VPEOpt_IWX3 11
217 #define CP0VPEOpt_IWX2 10
218 #define CP0VPEOpt_IWX1 9
219 #define CP0VPEOpt_IWX0 8
220 #define CP0VPEOpt_DWX7 7
221 #define CP0VPEOpt_DWX6 6
222 #define CP0VPEOpt_DWX5 5
223 #define CP0VPEOpt_DWX4 4
224 #define CP0VPEOpt_DWX3 3
225 #define CP0VPEOpt_DWX2 2
226 #define CP0VPEOpt_DWX1 1
227 #define CP0VPEOpt_DWX0 0
228 target_ulong CP0_EntryLo0;
229 target_ulong CP0_EntryLo1;
230 target_ulong CP0_Context;
231 int32_t CP0_PageMask;
232 int32_t CP0_PageGrain;
233 int32_t CP0_Wired;
234 int32_t CP0_SRSConf0_rw_bitmask;
235 int32_t CP0_SRSConf0;
236 #define CP0SRSC0_M 31
237 #define CP0SRSC0_SRS3 20
238 #define CP0SRSC0_SRS2 10
239 #define CP0SRSC0_SRS1 0
240 int32_t CP0_SRSConf1_rw_bitmask;
241 int32_t CP0_SRSConf1;
242 #define CP0SRSC1_M 31
243 #define CP0SRSC1_SRS6 20
244 #define CP0SRSC1_SRS5 10
245 #define CP0SRSC1_SRS4 0
246 int32_t CP0_SRSConf2_rw_bitmask;
247 int32_t CP0_SRSConf2;
248 #define CP0SRSC2_M 31
249 #define CP0SRSC2_SRS9 20
250 #define CP0SRSC2_SRS8 10
251 #define CP0SRSC2_SRS7 0
252 int32_t CP0_SRSConf3_rw_bitmask;
253 int32_t CP0_SRSConf3;
254 #define CP0SRSC3_M 31
255 #define CP0SRSC3_SRS12 20
256 #define CP0SRSC3_SRS11 10
257 #define CP0SRSC3_SRS10 0
258 int32_t CP0_SRSConf4_rw_bitmask;
259 int32_t CP0_SRSConf4;
260 #define CP0SRSC4_SRS15 20
261 #define CP0SRSC4_SRS14 10
262 #define CP0SRSC4_SRS13 0
263 int32_t CP0_HWREna;
264 target_ulong CP0_BadVAddr;
265 int32_t CP0_Count;
266 target_ulong CP0_EntryHi;
267 int32_t CP0_Compare;
268 int32_t CP0_Status;
269 #define CP0St_CU3 31
270 #define CP0St_CU2 30
271 #define CP0St_CU1 29
272 #define CP0St_CU0 28
273 #define CP0St_RP 27
274 #define CP0St_FR 26
275 #define CP0St_RE 25
276 #define CP0St_MX 24
277 #define CP0St_PX 23
278 #define CP0St_BEV 22
279 #define CP0St_TS 21
280 #define CP0St_SR 20
281 #define CP0St_NMI 19
282 #define CP0St_IM 8
283 #define CP0St_KX 7
284 #define CP0St_SX 6
285 #define CP0St_UX 5
286 #define CP0St_KSU 3
287 #define CP0St_ERL 2
288 #define CP0St_EXL 1
289 #define CP0St_IE 0
290 int32_t CP0_IntCtl;
291 #define CP0IntCtl_IPTI 29
292 #define CP0IntCtl_IPPC1 26
293 #define CP0IntCtl_VS 5
294 int32_t CP0_SRSCtl;
295 #define CP0SRSCtl_HSS 26
296 #define CP0SRSCtl_EICSS 18
297 #define CP0SRSCtl_ESS 12
298 #define CP0SRSCtl_PSS 6
299 #define CP0SRSCtl_CSS 0
300 int32_t CP0_SRSMap;
301 #define CP0SRSMap_SSV7 28
302 #define CP0SRSMap_SSV6 24
303 #define CP0SRSMap_SSV5 20
304 #define CP0SRSMap_SSV4 16
305 #define CP0SRSMap_SSV3 12
306 #define CP0SRSMap_SSV2 8
307 #define CP0SRSMap_SSV1 4
308 #define CP0SRSMap_SSV0 0
309 int32_t CP0_Cause;
310 #define CP0Ca_BD 31
311 #define CP0Ca_TI 30
312 #define CP0Ca_CE 28
313 #define CP0Ca_DC 27
314 #define CP0Ca_PCI 26
315 #define CP0Ca_IV 23
316 #define CP0Ca_WP 22
317 #define CP0Ca_IP 8
318 #define CP0Ca_IP_mask 0x0000FF00
319 #define CP0Ca_EC 2
320 target_ulong CP0_EPC;
321 int32_t CP0_PRid;
322 int32_t CP0_EBase;
323 int32_t CP0_Config0;
324 #define CP0C0_M 31
325 #define CP0C0_K23 28
326 #define CP0C0_KU 25
327 #define CP0C0_MDU 20
328 #define CP0C0_MM 17
329 #define CP0C0_BM 16
330 #define CP0C0_BE 15
331 #define CP0C0_AT 13
332 #define CP0C0_AR 10
333 #define CP0C0_MT 7
334 #define CP0C0_VI 3
335 #define CP0C0_K0 0
336 int32_t CP0_Config1;
337 #define CP0C1_M 31
338 #define CP0C1_MMU 25
339 #define CP0C1_IS 22
340 #define CP0C1_IL 19
341 #define CP0C1_IA 16
342 #define CP0C1_DS 13
343 #define CP0C1_DL 10
344 #define CP0C1_DA 7
345 #define CP0C1_C2 6
346 #define CP0C1_MD 5
347 #define CP0C1_PC 4
348 #define CP0C1_WR 3
349 #define CP0C1_CA 2
350 #define CP0C1_EP 1
351 #define CP0C1_FP 0
352 int32_t CP0_Config2;
353 #define CP0C2_M 31
354 #define CP0C2_TU 28
355 #define CP0C2_TS 24
356 #define CP0C2_TL 20
357 #define CP0C2_TA 16
358 #define CP0C2_SU 12
359 #define CP0C2_SS 8
360 #define CP0C2_SL 4
361 #define CP0C2_SA 0
362 int32_t CP0_Config3;
363 #define CP0C3_M 31
364 #define CP0C3_DSPP 10
365 #define CP0C3_LPA 7
366 #define CP0C3_VEIC 6
367 #define CP0C3_VInt 5
368 #define CP0C3_SP 4
369 #define CP0C3_MT 2
370 #define CP0C3_SM 1
371 #define CP0C3_TL 0
372 int32_t CP0_Config6;
373 int32_t CP0_Config7;
374 /* XXX: Maybe make LLAddr per-TC? */
375 target_ulong lladdr;
376 target_ulong llval;
377 target_ulong llnewval;
378 target_ulong llreg;
379 target_ulong CP0_LLAddr_rw_bitmask;
380 int CP0_LLAddr_shift;
381 target_ulong CP0_WatchLo[8];
382 int32_t CP0_WatchHi[8];
383 target_ulong CP0_XContext;
384 int32_t CP0_Framemask;
385 int32_t CP0_Debug;
386 #define CP0DB_DBD 31
387 #define CP0DB_DM 30
388 #define CP0DB_LSNM 28
389 #define CP0DB_Doze 27
390 #define CP0DB_Halt 26
391 #define CP0DB_CNT 25
392 #define CP0DB_IBEP 24
393 #define CP0DB_DBEP 21
394 #define CP0DB_IEXI 20
395 #define CP0DB_VER 15
396 #define CP0DB_DEC 10
397 #define CP0DB_SSt 8
398 #define CP0DB_DINT 5
399 #define CP0DB_DIB 4
400 #define CP0DB_DDBS 3
401 #define CP0DB_DDBL 2
402 #define CP0DB_DBp 1
403 #define CP0DB_DSS 0
404 target_ulong CP0_DEPC;
405 int32_t CP0_Performance0;
406 int32_t CP0_TagLo;
407 int32_t CP0_DataLo;
408 int32_t CP0_TagHi;
409 int32_t CP0_DataHi;
410 target_ulong CP0_ErrorEPC;
411 int32_t CP0_DESAVE;
412 /* We waste some space so we can handle shadow registers like TCs. */
413 TCState tcs[MIPS_SHADOW_SET_MAX];
414 CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
415 /* Qemu */
416 int error_code;
417 uint32_t hflags; /* CPU State */
418 /* TMASK defines different execution modes */
419 #define MIPS_HFLAG_TMASK 0x03FF
420 #define MIPS_HFLAG_MODE 0x0007 /* execution modes */
421 /* The KSU flags must be the lowest bits in hflags. The flag order
422 must be the same as defined for CP0 Status. This allows to use
423 the bits as the value of mmu_idx. */
424 #define MIPS_HFLAG_KSU 0x0003 /* kernel/supervisor/user mode mask */
425 #define MIPS_HFLAG_UM 0x0002 /* user mode flag */
426 #define MIPS_HFLAG_SM 0x0001 /* supervisor mode flag */
427 #define MIPS_HFLAG_KM 0x0000 /* kernel mode flag */
428 #define MIPS_HFLAG_DM 0x0004 /* Debug mode */
429 #define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */
430 #define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */
431 #define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */
432 #define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */
433 /* True if the MIPS IV COP1X instructions can be used. This also
434 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
435 and RSQRT.D. */
436 #define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */
437 #define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */
438 #define MIPS_HFLAG_UX 0x0200 /* 64-bit user mode */
439 /* If translation is interrupted between the branch instruction and
440 * the delay slot, record what type of branch it is so that we can
441 * resume translation properly. It might be possible to reduce
442 * this from three bits to two. */
443 #define MIPS_HFLAG_BMASK 0x1C00
444 #define MIPS_HFLAG_B 0x0400 /* Unconditional branch */
445 #define MIPS_HFLAG_BC 0x0800 /* Conditional branch */
446 #define MIPS_HFLAG_BL 0x0C00 /* Likely branch */
447 #define MIPS_HFLAG_BR 0x1000 /* branch to register (can't link TB) */
448 target_ulong btarget; /* Jump / branch target */
449 target_ulong bcond; /* Branch condition (if needed) */
450
451 int SYNCI_Step; /* Address step size for SYNCI */
452 int CCRes; /* Cycle count resolution/divisor */
453 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
454 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
455 int insn_flags; /* Supported instruction set */
456
457 target_ulong tls_value; /* For usermode emulation */
458
459 CPU_COMMON
460
461 CPUMIPSMVPContext *mvp;
462 CPUMIPSTLBContext *tlb;
463
464 const mips_def_t *cpu_model;
465 void *irq[8];
466 struct QEMUTimer *timer; /* Internal timer */
467 };
468
469 int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
470 target_ulong address, int rw, int access_type);
471 int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
472 target_ulong address, int rw, int access_type);
473 int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
474 target_ulong address, int rw, int access_type);
475 void r4k_helper_tlbwi (void);
476 void r4k_helper_tlbwr (void);
477 void r4k_helper_tlbp (void);
478 void r4k_helper_tlbr (void);
479 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
480
481 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
482 int unused, int size);
483
484 #define cpu_init cpu_mips_init
485 #define cpu_exec cpu_mips_exec
486 #define cpu_gen_code cpu_mips_gen_code
487 #define cpu_signal_handler cpu_mips_signal_handler
488 #define cpu_list mips_cpu_list
489
490 #define CPU_SAVE_VERSION 3
491
492 /* MMU modes definitions. We carefully match the indices with our
493 hflags layout. */
494 #define MMU_MODE0_SUFFIX _kernel
495 #define MMU_MODE1_SUFFIX _super
496 #define MMU_MODE2_SUFFIX _user
497 #define MMU_USER_IDX 2
cpu_mmu_index(CPUState * env)498 static inline int cpu_mmu_index (CPUState *env)
499 {
500 return env->hflags & MIPS_HFLAG_KSU;
501 }
502
is_cpu_user(CPUState * env)503 static inline int is_cpu_user (CPUState *env)
504 {
505 #ifdef CONFIG_USER_ONLY
506 return 1;
507 #else
508 return ((env->CP0_Status &
509 ((3 << CP0St_KSU) | (1 << CP0St_ERL) | (1 << CP0St_EXL))) == (3 << CP0St_KSU));
510 #endif // CONFIG_USER_ONLY
511 }
512
cpu_clone_regs(CPUState * env,target_ulong newsp)513 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
514 {
515 if (newsp)
516 env->active_tc.gpr[29] = newsp;
517 env->active_tc.gpr[7] = 0;
518 env->active_tc.gpr[2] = 0;
519 }
520
521 #include "cpu-all.h"
522 #include "exec-all.h"
523
524 /* Memory access type :
525 * may be needed for precise access rights control and precise exceptions.
526 */
527 enum {
528 /* 1 bit to define user level / supervisor access */
529 ACCESS_USER = 0x00,
530 ACCESS_SUPER = 0x01,
531 /* 1 bit to indicate direction */
532 ACCESS_STORE = 0x02,
533 /* Type of instruction that generated the access */
534 ACCESS_CODE = 0x10, /* Code fetch access */
535 ACCESS_INT = 0x20, /* Integer load/store access */
536 ACCESS_FLOAT = 0x30, /* floating point load/store access */
537 };
538
539 /* Exceptions */
540 enum {
541 EXCP_NONE = -1,
542 EXCP_RESET = 0,
543 EXCP_SRESET,
544 EXCP_DSS,
545 EXCP_DINT,
546 EXCP_DDBL,
547 EXCP_DDBS,
548 EXCP_NMI,
549 EXCP_MCHECK,
550 EXCP_EXT_INTERRUPT, /* 8 */
551 EXCP_DFWATCH,
552 EXCP_DIB,
553 EXCP_IWATCH,
554 EXCP_AdEL,
555 EXCP_AdES,
556 EXCP_TLBF,
557 EXCP_IBE,
558 EXCP_DBp, /* 16 */
559 EXCP_SYSCALL,
560 EXCP_BREAK,
561 EXCP_CpU,
562 EXCP_RI,
563 EXCP_OVERFLOW,
564 EXCP_TRAP,
565 EXCP_FPE,
566 EXCP_DWATCH, /* 24 */
567 EXCP_LTLBL,
568 EXCP_TLBL,
569 EXCP_TLBS,
570 EXCP_DBE,
571 EXCP_THREAD,
572 EXCP_MDMX,
573 EXCP_C2E,
574 EXCP_CACHE, /* 32 */
575
576 EXCP_LAST = EXCP_CACHE,
577 };
578 /* Dummy exception for conditional stores. */
579 #define EXCP_SC 0x100
580
581 int cpu_mips_exec(CPUMIPSState *s);
582 CPUMIPSState *cpu_mips_init(const char *cpu_model);
583 //~ uint32_t cpu_mips_get_clock (void);
584 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
585
586 /* mips_timer.c */
587 uint32_t cpu_mips_get_random (CPUState *env);
588 uint32_t cpu_mips_get_count (CPUState *env);
589 void cpu_mips_store_count (CPUState *env, uint32_t value);
590 void cpu_mips_store_compare (CPUState *env, uint32_t value);
591 void cpu_mips_start_count(CPUState *env);
592 void cpu_mips_stop_count(CPUState *env);
593
594 /* mips_int.c */
595 void cpu_mips_update_irq (CPUState *env);
596
597 /* helper.c */
598 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
599 int mmu_idx, int is_softmmu);
600 #define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
601 void do_interrupt (CPUState *env);
602 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
603 target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address,
604 int rw);
605
cpu_pc_from_tb(CPUState * env,TranslationBlock * tb)606 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
607 {
608 env->active_tc.PC = tb->pc;
609 env->hflags &= ~MIPS_HFLAG_BMASK;
610 env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
611 }
612
cpu_get_tb_cpu_state(CPUState * env,target_ulong * pc,target_ulong * cs_base,int * flags)613 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
614 target_ulong *cs_base, int *flags)
615 {
616 *pc = env->active_tc.PC;
617 *cs_base = 0;
618 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
619 }
620
cpu_set_tls(CPUState * env,target_ulong newtls)621 static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
622 {
623 env->tls_value = newtls;
624 }
625
626 #endif /* !defined (__MIPS_CPU_H__) */
627