1 //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the ARM target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16
17 #ifndef ARMBASEINFO_H
18 #define ARMBASEINFO_H
19
20 #include "ARMMCTargetDesc.h"
21 #include "llvm/Support/ErrorHandling.h"
22
23 namespace llvm {
24
25 // Enums corresponding to ARM condition codes
26 namespace ARMCC {
27 // The CondCodes constants map directly to the 4-bit encoding of the
28 // condition field for predicated instructions.
29 enum CondCodes { // Meaning (integer) Meaning (floating-point)
30 EQ, // Equal Equal
31 NE, // Not equal Not equal, or unordered
32 HS, // Carry set >, ==, or unordered
33 LO, // Carry clear Less than
34 MI, // Minus, negative Less than
35 PL, // Plus, positive or zero >, ==, or unordered
36 VS, // Overflow Unordered
37 VC, // No overflow Not unordered
38 HI, // Unsigned higher Greater than, or unordered
39 LS, // Unsigned lower or same Less than or equal
40 GE, // Greater than or equal Greater than or equal
41 LT, // Less than Less than, or unordered
42 GT, // Greater than Greater than
43 LE, // Less than or equal <, ==, or unordered
44 AL // Always (unconditional) Always (unconditional)
45 };
46
getOppositeCondition(CondCodes CC)47 inline static CondCodes getOppositeCondition(CondCodes CC) {
48 switch (CC) {
49 default: llvm_unreachable("Unknown condition code");
50 case EQ: return NE;
51 case NE: return EQ;
52 case HS: return LO;
53 case LO: return HS;
54 case MI: return PL;
55 case PL: return MI;
56 case VS: return VC;
57 case VC: return VS;
58 case HI: return LS;
59 case LS: return HI;
60 case GE: return LT;
61 case LT: return GE;
62 case GT: return LE;
63 case LE: return GT;
64 }
65 }
66 } // namespace ARMCC
67
ARMCondCodeToString(ARMCC::CondCodes CC)68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
69 switch (CC) {
70 case ARMCC::EQ: return "eq";
71 case ARMCC::NE: return "ne";
72 case ARMCC::HS: return "hs";
73 case ARMCC::LO: return "lo";
74 case ARMCC::MI: return "mi";
75 case ARMCC::PL: return "pl";
76 case ARMCC::VS: return "vs";
77 case ARMCC::VC: return "vc";
78 case ARMCC::HI: return "hi";
79 case ARMCC::LS: return "ls";
80 case ARMCC::GE: return "ge";
81 case ARMCC::LT: return "lt";
82 case ARMCC::GT: return "gt";
83 case ARMCC::LE: return "le";
84 case ARMCC::AL: return "al";
85 }
86 llvm_unreachable("Unknown condition code");
87 }
88
89 namespace ARM_PROC {
90 enum IMod {
91 IE = 2,
92 ID = 3
93 };
94
95 enum IFlags {
96 F = 1,
97 I = 2,
98 A = 4
99 };
100
IFlagsToString(unsigned val)101 inline static const char *IFlagsToString(unsigned val) {
102 switch (val) {
103 default: llvm_unreachable("Unknown iflags operand");
104 case F: return "f";
105 case I: return "i";
106 case A: return "a";
107 }
108 }
109
IModToString(unsigned val)110 inline static const char *IModToString(unsigned val) {
111 switch (val) {
112 default: llvm_unreachable("Unknown imod operand");
113 case IE: return "ie";
114 case ID: return "id";
115 }
116 }
117 }
118
119 namespace ARM_MB {
120 // The Memory Barrier Option constants map directly to the 4-bit encoding of
121 // the option field for memory barrier operations.
122 enum MemBOpt {
123 SY = 15,
124 ST = 14,
125 ISH = 11,
126 ISHST = 10,
127 NSH = 7,
128 NSHST = 6,
129 OSH = 3,
130 OSHST = 2
131 };
132
MemBOptToString(unsigned val)133 inline static const char *MemBOptToString(unsigned val) {
134 switch (val) {
135 default: llvm_unreachable("Unknown memory operation");
136 case SY: return "sy";
137 case ST: return "st";
138 case ISH: return "ish";
139 case ISHST: return "ishst";
140 case NSH: return "nsh";
141 case NSHST: return "nshst";
142 case OSH: return "osh";
143 case OSHST: return "oshst";
144 }
145 }
146 } // namespace ARM_MB
147
148 /// getARMRegisterNumbering - Given the enum value for some register, e.g.
149 /// ARM::LR, return the number that it corresponds to (e.g. 14).
getARMRegisterNumbering(unsigned Reg)150 inline static unsigned getARMRegisterNumbering(unsigned Reg) {
151 using namespace ARM;
152 switch (Reg) {
153 default:
154 llvm_unreachable("Unknown ARM register!");
155 case R0: case S0: case D0: case Q0: return 0;
156 case R1: case S1: case D1: case Q1: return 1;
157 case R2: case S2: case D2: case Q2: return 2;
158 case R3: case S3: case D3: case Q3: return 3;
159 case R4: case S4: case D4: case Q4: return 4;
160 case R5: case S5: case D5: case Q5: return 5;
161 case R6: case S6: case D6: case Q6: return 6;
162 case R7: case S7: case D7: case Q7: return 7;
163 case R8: case S8: case D8: case Q8: return 8;
164 case R9: case S9: case D9: case Q9: return 9;
165 case R10: case S10: case D10: case Q10: return 10;
166 case R11: case S11: case D11: case Q11: return 11;
167 case R12: case S12: case D12: case Q12: return 12;
168 case SP: case S13: case D13: case Q13: return 13;
169 case LR: case S14: case D14: case Q14: return 14;
170 case PC: case S15: case D15: case Q15: return 15;
171
172 case S16: case D16: return 16;
173 case S17: case D17: return 17;
174 case S18: case D18: return 18;
175 case S19: case D19: return 19;
176 case S20: case D20: return 20;
177 case S21: case D21: return 21;
178 case S22: case D22: return 22;
179 case S23: case D23: return 23;
180 case S24: case D24: return 24;
181 case S25: case D25: return 25;
182 case S26: case D26: return 26;
183 case S27: case D27: return 27;
184 case S28: case D28: return 28;
185 case S29: case D29: return 29;
186 case S30: case D30: return 30;
187 case S31: case D31: return 31;
188
189 // Composite registers use the regnum of the first register in the list.
190 /* Q0 */ case D0_D2: return 0;
191 case D1_D2: case D1_D3: return 1;
192 /* Q1 */ case D2_D4: return 2;
193 case D3_D4: case D3_D5: return 3;
194 /* Q2 */ case D4_D6: return 4;
195 case D5_D6: case D5_D7: return 5;
196 /* Q3 */ case D6_D8: return 6;
197 case D7_D8: case D7_D9: return 7;
198 /* Q4 */ case D8_D10: return 8;
199 case D9_D10: case D9_D11: return 9;
200 /* Q5 */ case D10_D12: return 10;
201 case D11_D12: case D11_D13: return 11;
202 /* Q6 */ case D12_D14: return 12;
203 case D13_D14: case D13_D15: return 13;
204 /* Q7 */ case D14_D16: return 14;
205 case D15_D16: case D15_D17: return 15;
206 /* Q8 */ case D16_D18: return 16;
207 case D17_D18: case D17_D19: return 17;
208 /* Q9 */ case D18_D20: return 18;
209 case D19_D20: case D19_D21: return 19;
210 /* Q10 */ case D20_D22: return 20;
211 case D21_D22: case D21_D23: return 21;
212 /* Q11 */ case D22_D24: return 22;
213 case D23_D24: case D23_D25: return 23;
214 /* Q12 */ case D24_D26: return 24;
215 case D25_D26: case D25_D27: return 25;
216 /* Q13 */ case D26_D28: return 26;
217 case D27_D28: case D27_D29: return 27;
218 /* Q14 */ case D28_D30: return 28;
219 case D29_D30: case D29_D31: return 29;
220 /* Q15 */
221 }
222 }
223
224 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
225 ///
isARMLowRegister(unsigned Reg)226 static inline bool isARMLowRegister(unsigned Reg) {
227 using namespace ARM;
228 switch (Reg) {
229 case R0: case R1: case R2: case R3:
230 case R4: case R5: case R6: case R7:
231 return true;
232 default:
233 return false;
234 }
235 }
236
237 /// ARMII - This namespace holds all of the target specific flags that
238 /// instruction info tracks.
239 ///
240 namespace ARMII {
241
242 /// ARM Index Modes
243 enum IndexMode {
244 IndexModeNone = 0,
245 IndexModePre = 1,
246 IndexModePost = 2,
247 IndexModeUpd = 3
248 };
249
250 /// ARM Addressing Modes
251 enum AddrMode {
252 AddrModeNone = 0,
253 AddrMode1 = 1,
254 AddrMode2 = 2,
255 AddrMode3 = 3,
256 AddrMode4 = 4,
257 AddrMode5 = 5,
258 AddrMode6 = 6,
259 AddrModeT1_1 = 7,
260 AddrModeT1_2 = 8,
261 AddrModeT1_4 = 9,
262 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
263 AddrModeT2_i12 = 11,
264 AddrModeT2_i8 = 12,
265 AddrModeT2_so = 13,
266 AddrModeT2_pc = 14, // +/- i12 for pc relative data
267 AddrModeT2_i8s4 = 15, // i8 * 4
268 AddrMode_i12 = 16
269 };
270
AddrModeToString(AddrMode addrmode)271 inline static const char *AddrModeToString(AddrMode addrmode) {
272 switch (addrmode) {
273 case AddrModeNone: return "AddrModeNone";
274 case AddrMode1: return "AddrMode1";
275 case AddrMode2: return "AddrMode2";
276 case AddrMode3: return "AddrMode3";
277 case AddrMode4: return "AddrMode4";
278 case AddrMode5: return "AddrMode5";
279 case AddrMode6: return "AddrMode6";
280 case AddrModeT1_1: return "AddrModeT1_1";
281 case AddrModeT1_2: return "AddrModeT1_2";
282 case AddrModeT1_4: return "AddrModeT1_4";
283 case AddrModeT1_s: return "AddrModeT1_s";
284 case AddrModeT2_i12: return "AddrModeT2_i12";
285 case AddrModeT2_i8: return "AddrModeT2_i8";
286 case AddrModeT2_so: return "AddrModeT2_so";
287 case AddrModeT2_pc: return "AddrModeT2_pc";
288 case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
289 case AddrMode_i12: return "AddrMode_i12";
290 }
291 }
292
293 /// Target Operand Flag enum.
294 enum TOF {
295 //===------------------------------------------------------------------===//
296 // ARM Specific MachineOperand flags.
297
298 MO_NO_FLAG,
299
300 /// MO_LO16 - On a symbol operand, this represents a relocation containing
301 /// lower 16 bit of the address. Used only via movw instruction.
302 MO_LO16,
303
304 /// MO_HI16 - On a symbol operand, this represents a relocation containing
305 /// higher 16 bit of the address. Used only via movt instruction.
306 MO_HI16,
307
308 /// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a
309 /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
310 /// i.e. "FOO$non_lazy_ptr".
311 /// Used only via movw instruction.
312 MO_LO16_NONLAZY,
313
314 /// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a
315 /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
316 /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction.
317 MO_HI16_NONLAZY,
318
319 /// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
320 /// relocation containing lower 16 bit of the PC relative address of the
321 /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
322 /// Used only via movw instruction.
323 MO_LO16_NONLAZY_PIC,
324
325 /// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
326 /// relocation containing lower 16 bit of the PC relative address of the
327 /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
328 /// Used only via movt instruction.
329 MO_HI16_NONLAZY_PIC,
330
331 /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
332 /// call operand.
333 MO_PLT
334 };
335
336 enum {
337 //===------------------------------------------------------------------===//
338 // Instruction Flags.
339
340 //===------------------------------------------------------------------===//
341 // This four-bit field describes the addressing mode used.
342 AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
343
344 // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
345 // and store ops only. Generic "updating" flag is used for ld/st multiple.
346 // The index mode enums are declared in ARMBaseInfo.h
347 IndexModeShift = 5,
348 IndexModeMask = 3 << IndexModeShift,
349
350 //===------------------------------------------------------------------===//
351 // Instruction encoding formats.
352 //
353 FormShift = 7,
354 FormMask = 0x3f << FormShift,
355
356 // Pseudo instructions
357 Pseudo = 0 << FormShift,
358
359 // Multiply instructions
360 MulFrm = 1 << FormShift,
361
362 // Branch instructions
363 BrFrm = 2 << FormShift,
364 BrMiscFrm = 3 << FormShift,
365
366 // Data Processing instructions
367 DPFrm = 4 << FormShift,
368 DPSoRegFrm = 5 << FormShift,
369
370 // Load and Store
371 LdFrm = 6 << FormShift,
372 StFrm = 7 << FormShift,
373 LdMiscFrm = 8 << FormShift,
374 StMiscFrm = 9 << FormShift,
375 LdStMulFrm = 10 << FormShift,
376
377 LdStExFrm = 11 << FormShift,
378
379 // Miscellaneous arithmetic instructions
380 ArithMiscFrm = 12 << FormShift,
381 SatFrm = 13 << FormShift,
382
383 // Extend instructions
384 ExtFrm = 14 << FormShift,
385
386 // VFP formats
387 VFPUnaryFrm = 15 << FormShift,
388 VFPBinaryFrm = 16 << FormShift,
389 VFPConv1Frm = 17 << FormShift,
390 VFPConv2Frm = 18 << FormShift,
391 VFPConv3Frm = 19 << FormShift,
392 VFPConv4Frm = 20 << FormShift,
393 VFPConv5Frm = 21 << FormShift,
394 VFPLdStFrm = 22 << FormShift,
395 VFPLdStMulFrm = 23 << FormShift,
396 VFPMiscFrm = 24 << FormShift,
397
398 // Thumb format
399 ThumbFrm = 25 << FormShift,
400
401 // Miscelleaneous format
402 MiscFrm = 26 << FormShift,
403
404 // NEON formats
405 NGetLnFrm = 27 << FormShift,
406 NSetLnFrm = 28 << FormShift,
407 NDupFrm = 29 << FormShift,
408 NLdStFrm = 30 << FormShift,
409 N1RegModImmFrm= 31 << FormShift,
410 N2RegFrm = 32 << FormShift,
411 NVCVTFrm = 33 << FormShift,
412 NVDupLnFrm = 34 << FormShift,
413 N2RegVShLFrm = 35 << FormShift,
414 N2RegVShRFrm = 36 << FormShift,
415 N3RegFrm = 37 << FormShift,
416 N3RegVShFrm = 38 << FormShift,
417 NVExtFrm = 39 << FormShift,
418 NVMulSLFrm = 40 << FormShift,
419 NVTBLFrm = 41 << FormShift,
420
421 //===------------------------------------------------------------------===//
422 // Misc flags.
423
424 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
425 // it doesn't have a Rn operand.
426 UnaryDP = 1 << 13,
427
428 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
429 // a 16-bit Thumb instruction if certain conditions are met.
430 Xform16Bit = 1 << 14,
431
432 // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
433 // instruction. Used by the parser to determine whether to require the 'S'
434 // suffix on the mnemonic (when not in an IT block) or preclude it (when
435 // in an IT block).
436 ThumbArithFlagSetting = 1 << 18,
437
438 //===------------------------------------------------------------------===//
439 // Code domain.
440 DomainShift = 15,
441 DomainMask = 7 << DomainShift,
442 DomainGeneral = 0 << DomainShift,
443 DomainVFP = 1 << DomainShift,
444 DomainNEON = 2 << DomainShift,
445 DomainNEONA8 = 4 << DomainShift,
446
447 //===------------------------------------------------------------------===//
448 // Field shifts - such shifts are used to set field while generating
449 // machine instructions.
450 //
451 // FIXME: This list will need adjusting/fixing as the MC code emitter
452 // takes shape and the ARMCodeEmitter.cpp bits go away.
453 ShiftTypeShift = 4,
454
455 M_BitShift = 5,
456 ShiftImmShift = 5,
457 ShiftShift = 7,
458 N_BitShift = 7,
459 ImmHiShift = 8,
460 SoRotImmShift = 8,
461 RegRsShift = 8,
462 ExtRotImmShift = 10,
463 RegRdLoShift = 12,
464 RegRdShift = 12,
465 RegRdHiShift = 16,
466 RegRnShift = 16,
467 S_BitShift = 20,
468 W_BitShift = 21,
469 AM3_I_BitShift = 22,
470 D_BitShift = 22,
471 U_BitShift = 23,
472 P_BitShift = 24,
473 I_BitShift = 25,
474 CondShift = 28
475 };
476
477 } // end namespace ARMII
478
479 } // end namespace llvm;
480
481 #endif
482