1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
16 // types.
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
20 //
21 //===----------------------------------------------------------------------===//
22
23 #include "LegalizeTypes.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
27 using namespace llvm;
28
29 //===----------------------------------------------------------------------===//
30 // Result Vector Scalarization: <1 x ty> -> ty.
31 //===----------------------------------------------------------------------===//
32
ScalarizeVectorResult(SDNode * N,unsigned ResNo)33 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
34 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
35 N->dump(&DAG);
36 dbgs() << "\n");
37 SDValue R = SDValue();
38
39 switch (N->getOpcode()) {
40 default:
41 #ifndef NDEBUG
42 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
43 N->dump(&DAG);
44 dbgs() << "\n";
45 #endif
46 report_fatal_error("Do not know how to scalarize the result of this "
47 "operator!\n");
48
49 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
51 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
67 case ISD::ANY_EXTEND:
68 case ISD::CTLZ:
69 case ISD::CTPOP:
70 case ISD::CTTZ:
71 case ISD::FABS:
72 case ISD::FCEIL:
73 case ISD::FCOS:
74 case ISD::FEXP:
75 case ISD::FEXP2:
76 case ISD::FFLOOR:
77 case ISD::FLOG:
78 case ISD::FLOG10:
79 case ISD::FLOG2:
80 case ISD::FNEARBYINT:
81 case ISD::FNEG:
82 case ISD::FP_EXTEND:
83 case ISD::FP_TO_SINT:
84 case ISD::FP_TO_UINT:
85 case ISD::FRINT:
86 case ISD::FSIN:
87 case ISD::FSQRT:
88 case ISD::FTRUNC:
89 case ISD::SIGN_EXTEND:
90 case ISD::SINT_TO_FP:
91 case ISD::TRUNCATE:
92 case ISD::UINT_TO_FP:
93 case ISD::ZERO_EXTEND:
94 R = ScalarizeVecRes_UnaryOp(N);
95 break;
96
97 case ISD::ADD:
98 case ISD::AND:
99 case ISD::FADD:
100 case ISD::FDIV:
101 case ISD::FMUL:
102 case ISD::FPOW:
103 case ISD::FREM:
104 case ISD::FSUB:
105 case ISD::MUL:
106 case ISD::OR:
107 case ISD::SDIV:
108 case ISD::SREM:
109 case ISD::SUB:
110 case ISD::UDIV:
111 case ISD::UREM:
112 case ISD::XOR:
113 case ISD::SHL:
114 case ISD::SRA:
115 case ISD::SRL:
116 R = ScalarizeVecRes_BinOp(N);
117 break;
118 }
119
120 // If R is null, the sub-method took care of registering the result.
121 if (R.getNode())
122 SetScalarizedVector(SDValue(N, ResNo), R);
123 }
124
ScalarizeVecRes_BinOp(SDNode * N)125 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
126 SDValue LHS = GetScalarizedVector(N->getOperand(0));
127 SDValue RHS = GetScalarizedVector(N->getOperand(1));
128 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
129 LHS.getValueType(), LHS, RHS);
130 }
131
ScalarizeVecRes_MERGE_VALUES(SDNode * N,unsigned ResNo)132 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
133 unsigned ResNo) {
134 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
135 return GetScalarizedVector(Op);
136 }
137
ScalarizeVecRes_BITCAST(SDNode * N)138 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
139 EVT NewVT = N->getValueType(0).getVectorElementType();
140 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
141 NewVT, N->getOperand(0));
142 }
143
ScalarizeVecRes_CONVERT_RNDSAT(SDNode * N)144 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
145 EVT NewVT = N->getValueType(0).getVectorElementType();
146 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
147 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
148 Op0, DAG.getValueType(NewVT),
149 DAG.getValueType(Op0.getValueType()),
150 N->getOperand(3),
151 N->getOperand(4),
152 cast<CvtRndSatSDNode>(N)->getCvtCode());
153 }
154
ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode * N)155 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
156 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
157 N->getValueType(0).getVectorElementType(),
158 N->getOperand(0), N->getOperand(1));
159 }
160
ScalarizeVecRes_FP_ROUND(SDNode * N)161 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
162 EVT NewVT = N->getValueType(0).getVectorElementType();
163 SDValue Op = GetScalarizedVector(N->getOperand(0));
164 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(),
165 NewVT, Op, N->getOperand(1));
166 }
167
ScalarizeVecRes_FPOWI(SDNode * N)168 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
169 SDValue Op = GetScalarizedVector(N->getOperand(0));
170 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
171 Op.getValueType(), Op, N->getOperand(1));
172 }
173
ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode * N)174 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
175 // The value to insert may have a wider type than the vector element type,
176 // so be sure to truncate it to the element type if necessary.
177 SDValue Op = N->getOperand(1);
178 EVT EltVT = N->getValueType(0).getVectorElementType();
179 if (Op.getValueType() != EltVT)
180 // FIXME: Can this happen for floating point types?
181 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
182 return Op;
183 }
184
ScalarizeVecRes_LOAD(LoadSDNode * N)185 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
186 assert(N->isUnindexed() && "Indexed vector load?");
187
188 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
189 N->getExtensionType(),
190 N->getValueType(0).getVectorElementType(),
191 N->getDebugLoc(),
192 N->getChain(), N->getBasePtr(),
193 DAG.getUNDEF(N->getBasePtr().getValueType()),
194 N->getPointerInfo(),
195 N->getMemoryVT().getVectorElementType(),
196 N->isVolatile(), N->isNonTemporal(),
197 N->isInvariant(), N->getOriginalAlignment());
198
199 // Legalized the chain result - switch anything that used the old chain to
200 // use the new one.
201 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
202 return Result;
203 }
204
ScalarizeVecRes_UnaryOp(SDNode * N)205 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
206 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
207 EVT DestVT = N->getValueType(0).getVectorElementType();
208 SDValue Op = GetScalarizedVector(N->getOperand(0));
209 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
210 }
211
ScalarizeVecRes_InregOp(SDNode * N)212 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
213 EVT EltVT = N->getValueType(0).getVectorElementType();
214 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
215 SDValue LHS = GetScalarizedVector(N->getOperand(0));
216 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT,
217 LHS, DAG.getValueType(ExtVT));
218 }
219
ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode * N)220 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
221 // If the operand is wider than the vector element type then it is implicitly
222 // truncated. Make that explicit here.
223 EVT EltVT = N->getValueType(0).getVectorElementType();
224 SDValue InOp = N->getOperand(0);
225 if (InOp.getValueType() != EltVT)
226 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
227 return InOp;
228 }
229
ScalarizeVecRes_VSELECT(SDNode * N)230 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
231 SDValue Cond = GetScalarizedVector(N->getOperand(0));
232 SDValue LHS = GetScalarizedVector(N->getOperand(1));
233 TargetLowering::BooleanContent ScalarBool = TLI.getBooleanContents(false);
234 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true);
235 if (ScalarBool != VecBool) {
236 EVT CondVT = Cond.getValueType();
237 switch (ScalarBool) {
238 case TargetLowering::UndefinedBooleanContent:
239 break;
240 case TargetLowering::ZeroOrOneBooleanContent:
241 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
242 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
243 // Vector read from all ones, scalar expects a single 1 so mask.
244 Cond = DAG.getNode(ISD::AND, N->getDebugLoc(), CondVT,
245 Cond, DAG.getConstant(1, CondVT));
246 break;
247 case TargetLowering::ZeroOrNegativeOneBooleanContent:
248 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
249 VecBool == TargetLowering::ZeroOrOneBooleanContent);
250 // Vector reads from a one, scalar from all ones so sign extend.
251 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), CondVT,
252 Cond, DAG.getValueType(MVT::i1));
253 break;
254 }
255 }
256 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
257 LHS.getValueType(), Cond, LHS,
258 GetScalarizedVector(N->getOperand(2)));
259 }
260
ScalarizeVecRes_SELECT(SDNode * N)261 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
262 SDValue LHS = GetScalarizedVector(N->getOperand(1));
263 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
264 LHS.getValueType(), N->getOperand(0), LHS,
265 GetScalarizedVector(N->getOperand(2)));
266 }
267
ScalarizeVecRes_SELECT_CC(SDNode * N)268 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
269 SDValue LHS = GetScalarizedVector(N->getOperand(2));
270 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
271 N->getOperand(0), N->getOperand(1),
272 LHS, GetScalarizedVector(N->getOperand(3)),
273 N->getOperand(4));
274 }
275
ScalarizeVecRes_SETCC(SDNode * N)276 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
277 assert(N->getValueType(0).isVector() ==
278 N->getOperand(0).getValueType().isVector() &&
279 "Scalar/Vector type mismatch");
280
281 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
282
283 SDValue LHS = GetScalarizedVector(N->getOperand(0));
284 SDValue RHS = GetScalarizedVector(N->getOperand(1));
285 DebugLoc DL = N->getDebugLoc();
286
287 // Turn it into a scalar SETCC.
288 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
289 }
290
ScalarizeVecRes_UNDEF(SDNode * N)291 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
292 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
293 }
294
ScalarizeVecRes_VECTOR_SHUFFLE(SDNode * N)295 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
296 // Figure out if the scalar is the LHS or RHS and return it.
297 SDValue Arg = N->getOperand(2).getOperand(0);
298 if (Arg.getOpcode() == ISD::UNDEF)
299 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
300 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
301 return GetScalarizedVector(N->getOperand(Op));
302 }
303
ScalarizeVecRes_VSETCC(SDNode * N)304 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
305 assert(N->getValueType(0).isVector() &&
306 N->getOperand(0).getValueType().isVector() &&
307 "Operand types must be vectors");
308
309 SDValue LHS = GetScalarizedVector(N->getOperand(0));
310 SDValue RHS = GetScalarizedVector(N->getOperand(1));
311 EVT NVT = N->getValueType(0).getVectorElementType();
312 DebugLoc DL = N->getDebugLoc();
313
314 // Turn it into a scalar SETCC.
315 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
316 N->getOperand(2));
317 // Vectors may have a different boolean contents to scalars. Promote the
318 // value appropriately.
319 ISD::NodeType ExtendCode =
320 TargetLowering::getExtendForContent(TLI.getBooleanContents(true));
321 return DAG.getNode(ExtendCode, DL, NVT, Res);
322 }
323
324
325 //===----------------------------------------------------------------------===//
326 // Operand Vector Scalarization <1 x ty> -> ty.
327 //===----------------------------------------------------------------------===//
328
ScalarizeVectorOperand(SDNode * N,unsigned OpNo)329 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
330 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
331 N->dump(&DAG);
332 dbgs() << "\n");
333 SDValue Res = SDValue();
334
335 if (Res.getNode() == 0) {
336 switch (N->getOpcode()) {
337 default:
338 #ifndef NDEBUG
339 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
340 N->dump(&DAG);
341 dbgs() << "\n";
342 #endif
343 llvm_unreachable("Do not know how to scalarize this operator's operand!");
344 case ISD::BITCAST:
345 Res = ScalarizeVecOp_BITCAST(N);
346 break;
347 case ISD::CONCAT_VECTORS:
348 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
349 break;
350 case ISD::EXTRACT_VECTOR_ELT:
351 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
352 break;
353 case ISD::STORE:
354 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
355 break;
356 }
357 }
358
359 // If the result is null, the sub-method took care of registering results etc.
360 if (!Res.getNode()) return false;
361
362 // If the result is N, the sub-method updated N in place. Tell the legalizer
363 // core about this.
364 if (Res.getNode() == N)
365 return true;
366
367 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
368 "Invalid operand expansion");
369
370 ReplaceValueWith(SDValue(N, 0), Res);
371 return false;
372 }
373
374 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
375 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
ScalarizeVecOp_BITCAST(SDNode * N)376 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
377 SDValue Elt = GetScalarizedVector(N->getOperand(0));
378 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
379 N->getValueType(0), Elt);
380 }
381
382 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
383 /// use a BUILD_VECTOR instead.
ScalarizeVecOp_CONCAT_VECTORS(SDNode * N)384 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
385 SmallVector<SDValue, 8> Ops(N->getNumOperands());
386 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
387 Ops[i] = GetScalarizedVector(N->getOperand(i));
388 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
389 &Ops[0], Ops.size());
390 }
391
392 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
393 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
394 /// index.
ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode * N)395 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
396 SDValue Res = GetScalarizedVector(N->getOperand(0));
397 if (Res.getValueType() != N->getValueType(0))
398 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
399 Res);
400 return Res;
401 }
402
403 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
404 /// scalarized, it must be <1 x ty>. Just store the element.
ScalarizeVecOp_STORE(StoreSDNode * N,unsigned OpNo)405 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
406 assert(N->isUnindexed() && "Indexed store of one-element vector?");
407 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
408 DebugLoc dl = N->getDebugLoc();
409
410 if (N->isTruncatingStore())
411 return DAG.getTruncStore(N->getChain(), dl,
412 GetScalarizedVector(N->getOperand(1)),
413 N->getBasePtr(), N->getPointerInfo(),
414 N->getMemoryVT().getVectorElementType(),
415 N->isVolatile(), N->isNonTemporal(),
416 N->getAlignment());
417
418 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
419 N->getBasePtr(), N->getPointerInfo(),
420 N->isVolatile(), N->isNonTemporal(),
421 N->getOriginalAlignment());
422 }
423
424
425 //===----------------------------------------------------------------------===//
426 // Result Vector Splitting
427 //===----------------------------------------------------------------------===//
428
429 /// SplitVectorResult - This method is called when the specified result of the
430 /// specified node is found to need vector splitting. At this point, the node
431 /// may also have invalid operands or may have other results that need
432 /// legalization, we just know that (at least) one result needs vector
433 /// splitting.
SplitVectorResult(SDNode * N,unsigned ResNo)434 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
435 DEBUG(dbgs() << "Split node result: ";
436 N->dump(&DAG);
437 dbgs() << "\n");
438 SDValue Lo, Hi;
439
440 // See if the target wants to custom expand this node.
441 if (CustomLowerNode(N, N->getValueType(ResNo), true))
442 return;
443
444 switch (N->getOpcode()) {
445 default:
446 #ifndef NDEBUG
447 dbgs() << "SplitVectorResult #" << ResNo << ": ";
448 N->dump(&DAG);
449 dbgs() << "\n";
450 #endif
451 llvm_unreachable("Do not know how to split the result of this operator!");
452
453 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
454 case ISD::VSELECT:
455 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
456 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
457 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
458 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
459 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
460 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
461 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
462 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
463 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
464 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
465 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
466 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
467 case ISD::LOAD:
468 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
469 break;
470 case ISD::SETCC:
471 SplitVecRes_SETCC(N, Lo, Hi);
472 break;
473 case ISD::VECTOR_SHUFFLE:
474 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
475 break;
476
477 case ISD::ANY_EXTEND:
478 case ISD::CONVERT_RNDSAT:
479 case ISD::CTLZ:
480 case ISD::CTTZ:
481 case ISD::CTLZ_ZERO_UNDEF:
482 case ISD::CTTZ_ZERO_UNDEF:
483 case ISD::CTPOP:
484 case ISD::FABS:
485 case ISD::FCEIL:
486 case ISD::FCOS:
487 case ISD::FEXP:
488 case ISD::FEXP2:
489 case ISD::FFLOOR:
490 case ISD::FLOG:
491 case ISD::FLOG10:
492 case ISD::FLOG2:
493 case ISD::FNEARBYINT:
494 case ISD::FNEG:
495 case ISD::FP_EXTEND:
496 case ISD::FP_ROUND:
497 case ISD::FP_TO_SINT:
498 case ISD::FP_TO_UINT:
499 case ISD::FRINT:
500 case ISD::FSIN:
501 case ISD::FSQRT:
502 case ISD::FTRUNC:
503 case ISD::SIGN_EXTEND:
504 case ISD::SINT_TO_FP:
505 case ISD::TRUNCATE:
506 case ISD::UINT_TO_FP:
507 case ISD::ZERO_EXTEND:
508 SplitVecRes_UnaryOp(N, Lo, Hi);
509 break;
510
511 case ISD::ADD:
512 case ISD::SUB:
513 case ISD::MUL:
514 case ISD::FADD:
515 case ISD::FSUB:
516 case ISD::FMUL:
517 case ISD::SDIV:
518 case ISD::UDIV:
519 case ISD::FDIV:
520 case ISD::FPOW:
521 case ISD::AND:
522 case ISD::OR:
523 case ISD::XOR:
524 case ISD::SHL:
525 case ISD::SRA:
526 case ISD::SRL:
527 case ISD::UREM:
528 case ISD::SREM:
529 case ISD::FREM:
530 SplitVecRes_BinOp(N, Lo, Hi);
531 break;
532 }
533
534 // If Lo/Hi is null, the sub-method took care of registering results etc.
535 if (Lo.getNode())
536 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
537 }
538
SplitVecRes_BinOp(SDNode * N,SDValue & Lo,SDValue & Hi)539 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
540 SDValue &Hi) {
541 SDValue LHSLo, LHSHi;
542 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
543 SDValue RHSLo, RHSHi;
544 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
545 DebugLoc dl = N->getDebugLoc();
546
547 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
548 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
549 }
550
SplitVecRes_BITCAST(SDNode * N,SDValue & Lo,SDValue & Hi)551 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
552 SDValue &Hi) {
553 // We know the result is a vector. The input may be either a vector or a
554 // scalar value.
555 EVT LoVT, HiVT;
556 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
557 DebugLoc dl = N->getDebugLoc();
558
559 SDValue InOp = N->getOperand(0);
560 EVT InVT = InOp.getValueType();
561
562 // Handle some special cases efficiently.
563 switch (getTypeAction(InVT)) {
564 case TargetLowering::TypeLegal:
565 case TargetLowering::TypePromoteInteger:
566 case TargetLowering::TypeSoftenFloat:
567 case TargetLowering::TypeScalarizeVector:
568 case TargetLowering::TypeWidenVector:
569 break;
570 case TargetLowering::TypeExpandInteger:
571 case TargetLowering::TypeExpandFloat:
572 // A scalar to vector conversion, where the scalar needs expansion.
573 // If the vector is being split in two then we can just convert the
574 // expanded pieces.
575 if (LoVT == HiVT) {
576 GetExpandedOp(InOp, Lo, Hi);
577 if (TLI.isBigEndian())
578 std::swap(Lo, Hi);
579 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
580 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
581 return;
582 }
583 break;
584 case TargetLowering::TypeSplitVector:
585 // If the input is a vector that needs to be split, convert each split
586 // piece of the input now.
587 GetSplitVector(InOp, Lo, Hi);
588 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
589 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
590 return;
591 }
592
593 // In the general case, convert the input to an integer and split it by hand.
594 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
595 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
596 if (TLI.isBigEndian())
597 std::swap(LoIntVT, HiIntVT);
598
599 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
600
601 if (TLI.isBigEndian())
602 std::swap(Lo, Hi);
603 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
604 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
605 }
606
SplitVecRes_BUILD_VECTOR(SDNode * N,SDValue & Lo,SDValue & Hi)607 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
608 SDValue &Hi) {
609 EVT LoVT, HiVT;
610 DebugLoc dl = N->getDebugLoc();
611 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
612 unsigned LoNumElts = LoVT.getVectorNumElements();
613 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
614 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
615
616 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
617 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
618 }
619
SplitVecRes_CONCAT_VECTORS(SDNode * N,SDValue & Lo,SDValue & Hi)620 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
621 SDValue &Hi) {
622 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
623 DebugLoc dl = N->getDebugLoc();
624 unsigned NumSubvectors = N->getNumOperands() / 2;
625 if (NumSubvectors == 1) {
626 Lo = N->getOperand(0);
627 Hi = N->getOperand(1);
628 return;
629 }
630
631 EVT LoVT, HiVT;
632 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
633
634 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
635 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
636
637 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
638 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
639 }
640
SplitVecRes_EXTRACT_SUBVECTOR(SDNode * N,SDValue & Lo,SDValue & Hi)641 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
642 SDValue &Hi) {
643 SDValue Vec = N->getOperand(0);
644 SDValue Idx = N->getOperand(1);
645 DebugLoc dl = N->getDebugLoc();
646
647 EVT LoVT, HiVT;
648 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
649
650 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
651 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
652 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
653 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements()));
654 }
655
SplitVecRes_FPOWI(SDNode * N,SDValue & Lo,SDValue & Hi)656 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
657 SDValue &Hi) {
658 DebugLoc dl = N->getDebugLoc();
659 GetSplitVector(N->getOperand(0), Lo, Hi);
660 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
661 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
662 }
663
SplitVecRes_InregOp(SDNode * N,SDValue & Lo,SDValue & Hi)664 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
665 SDValue &Hi) {
666 SDValue LHSLo, LHSHi;
667 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
668 DebugLoc dl = N->getDebugLoc();
669
670 EVT LoVT, HiVT;
671 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT);
672
673 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
674 DAG.getValueType(LoVT));
675 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
676 DAG.getValueType(HiVT));
677 }
678
SplitVecRes_INSERT_VECTOR_ELT(SDNode * N,SDValue & Lo,SDValue & Hi)679 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
680 SDValue &Hi) {
681 SDValue Vec = N->getOperand(0);
682 SDValue Elt = N->getOperand(1);
683 SDValue Idx = N->getOperand(2);
684 DebugLoc dl = N->getDebugLoc();
685 GetSplitVector(Vec, Lo, Hi);
686
687 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
688 unsigned IdxVal = CIdx->getZExtValue();
689 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
690 if (IdxVal < LoNumElts)
691 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
692 Lo.getValueType(), Lo, Elt, Idx);
693 else
694 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
695 DAG.getIntPtrConstant(IdxVal - LoNumElts));
696 return;
697 }
698
699 // Spill the vector to the stack.
700 EVT VecVT = Vec.getValueType();
701 EVT EltVT = VecVT.getVectorElementType();
702 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
703 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
704 MachinePointerInfo(), false, false, 0);
705
706 // Store the new element. This may be larger than the vector element type,
707 // so use a truncating store.
708 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
709 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
710 unsigned Alignment =
711 TLI.getTargetData()->getPrefTypeAlignment(VecType);
712 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
713 false, false, 0);
714
715 // Load the Lo part from the stack slot.
716 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
717 false, false, false, 0);
718
719 // Increment the pointer to the other part.
720 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
721 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
722 DAG.getIntPtrConstant(IncrementSize));
723
724 // Load the Hi part from the stack slot.
725 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
726 false, false, false, MinAlign(Alignment, IncrementSize));
727 }
728
SplitVecRes_SCALAR_TO_VECTOR(SDNode * N,SDValue & Lo,SDValue & Hi)729 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
730 SDValue &Hi) {
731 EVT LoVT, HiVT;
732 DebugLoc dl = N->getDebugLoc();
733 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
734 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
735 Hi = DAG.getUNDEF(HiVT);
736 }
737
SplitVecRes_LOAD(LoadSDNode * LD,SDValue & Lo,SDValue & Hi)738 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
739 SDValue &Hi) {
740 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
741 EVT LoVT, HiVT;
742 DebugLoc dl = LD->getDebugLoc();
743 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
744
745 ISD::LoadExtType ExtType = LD->getExtensionType();
746 SDValue Ch = LD->getChain();
747 SDValue Ptr = LD->getBasePtr();
748 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
749 EVT MemoryVT = LD->getMemoryVT();
750 unsigned Alignment = LD->getOriginalAlignment();
751 bool isVolatile = LD->isVolatile();
752 bool isNonTemporal = LD->isNonTemporal();
753 bool isInvariant = LD->isInvariant();
754
755 EVT LoMemVT, HiMemVT;
756 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
757
758 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
759 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
760 isInvariant, Alignment);
761
762 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
763 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
764 DAG.getIntPtrConstant(IncrementSize));
765 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
766 LD->getPointerInfo().getWithOffset(IncrementSize),
767 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment);
768
769 // Build a factor node to remember that this load is independent of the
770 // other one.
771 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
772 Hi.getValue(1));
773
774 // Legalized the chain result - switch anything that used the old chain to
775 // use the new one.
776 ReplaceValueWith(SDValue(LD, 1), Ch);
777 }
778
SplitVecRes_SETCC(SDNode * N,SDValue & Lo,SDValue & Hi)779 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
780 assert(N->getValueType(0).isVector() &&
781 N->getOperand(0).getValueType().isVector() &&
782 "Operand types must be vectors");
783
784 EVT LoVT, HiVT;
785 DebugLoc DL = N->getDebugLoc();
786 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
787
788 // Split the input.
789 EVT InVT = N->getOperand(0).getValueType();
790 SDValue LL, LH, RL, RH;
791 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
792 LoVT.getVectorNumElements());
793 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
794 DAG.getIntPtrConstant(0));
795 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
796 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
797
798 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
799 DAG.getIntPtrConstant(0));
800 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
801 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
802
803 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
804 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
805 }
806
SplitVecRes_UnaryOp(SDNode * N,SDValue & Lo,SDValue & Hi)807 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
808 SDValue &Hi) {
809 // Get the dest types - they may not match the input types, e.g. int_to_fp.
810 EVT LoVT, HiVT;
811 DebugLoc dl = N->getDebugLoc();
812 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
813
814 // If the input also splits, handle it directly for a compile time speedup.
815 // Otherwise split it by hand.
816 EVT InVT = N->getOperand(0).getValueType();
817 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
818 GetSplitVector(N->getOperand(0), Lo, Hi);
819 } else {
820 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
821 LoVT.getVectorNumElements());
822 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
823 DAG.getIntPtrConstant(0));
824 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
825 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
826 }
827
828 if (N->getOpcode() == ISD::FP_ROUND) {
829 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
830 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
831 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
832 SDValue DTyOpLo = DAG.getValueType(LoVT);
833 SDValue DTyOpHi = DAG.getValueType(HiVT);
834 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
835 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
836 SDValue RndOp = N->getOperand(3);
837 SDValue SatOp = N->getOperand(4);
838 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
839 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
840 CvtCode);
841 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
842 CvtCode);
843 } else {
844 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
845 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
846 }
847 }
848
SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode * N,SDValue & Lo,SDValue & Hi)849 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
850 SDValue &Lo, SDValue &Hi) {
851 // The low and high parts of the original input give four input vectors.
852 SDValue Inputs[4];
853 DebugLoc dl = N->getDebugLoc();
854 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
855 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
856 EVT NewVT = Inputs[0].getValueType();
857 unsigned NewElts = NewVT.getVectorNumElements();
858
859 // If Lo or Hi uses elements from at most two of the four input vectors, then
860 // express it as a vector shuffle of those two inputs. Otherwise extract the
861 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
862 SmallVector<int, 16> Ops;
863 for (unsigned High = 0; High < 2; ++High) {
864 SDValue &Output = High ? Hi : Lo;
865
866 // Build a shuffle mask for the output, discovering on the fly which
867 // input vectors to use as shuffle operands (recorded in InputUsed).
868 // If building a suitable shuffle vector proves too hard, then bail
869 // out with useBuildVector set.
870 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
871 unsigned FirstMaskIdx = High * NewElts;
872 bool useBuildVector = false;
873 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
874 // The mask element. This indexes into the input.
875 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
876
877 // The input vector this mask element indexes into.
878 unsigned Input = (unsigned)Idx / NewElts;
879
880 if (Input >= array_lengthof(Inputs)) {
881 // The mask element does not index into any input vector.
882 Ops.push_back(-1);
883 continue;
884 }
885
886 // Turn the index into an offset from the start of the input vector.
887 Idx -= Input * NewElts;
888
889 // Find or create a shuffle vector operand to hold this input.
890 unsigned OpNo;
891 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
892 if (InputUsed[OpNo] == Input) {
893 // This input vector is already an operand.
894 break;
895 } else if (InputUsed[OpNo] == -1U) {
896 // Create a new operand for this input vector.
897 InputUsed[OpNo] = Input;
898 break;
899 }
900 }
901
902 if (OpNo >= array_lengthof(InputUsed)) {
903 // More than two input vectors used! Give up on trying to create a
904 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
905 useBuildVector = true;
906 break;
907 }
908
909 // Add the mask index for the new shuffle vector.
910 Ops.push_back(Idx + OpNo * NewElts);
911 }
912
913 if (useBuildVector) {
914 EVT EltVT = NewVT.getVectorElementType();
915 SmallVector<SDValue, 16> SVOps;
916
917 // Extract the input elements by hand.
918 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
919 // The mask element. This indexes into the input.
920 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
921
922 // The input vector this mask element indexes into.
923 unsigned Input = (unsigned)Idx / NewElts;
924
925 if (Input >= array_lengthof(Inputs)) {
926 // The mask element is "undef" or indexes off the end of the input.
927 SVOps.push_back(DAG.getUNDEF(EltVT));
928 continue;
929 }
930
931 // Turn the index into an offset from the start of the input vector.
932 Idx -= Input * NewElts;
933
934 // Extract the vector element by hand.
935 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
936 Inputs[Input], DAG.getIntPtrConstant(Idx)));
937 }
938
939 // Construct the Lo/Hi output using a BUILD_VECTOR.
940 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
941 } else if (InputUsed[0] == -1U) {
942 // No input vectors were used! The result is undefined.
943 Output = DAG.getUNDEF(NewVT);
944 } else {
945 SDValue Op0 = Inputs[InputUsed[0]];
946 // If only one input was used, use an undefined vector for the other.
947 SDValue Op1 = InputUsed[1] == -1U ?
948 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
949 // At least one input vector was used. Create a new shuffle vector.
950 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
951 }
952
953 Ops.clear();
954 }
955 }
956
957
958 //===----------------------------------------------------------------------===//
959 // Operand Vector Splitting
960 //===----------------------------------------------------------------------===//
961
962 /// SplitVectorOperand - This method is called when the specified operand of the
963 /// specified node is found to need vector splitting. At this point, all of the
964 /// result types of the node are known to be legal, but other operands of the
965 /// node may need legalization as well as the specified one.
SplitVectorOperand(SDNode * N,unsigned OpNo)966 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
967 DEBUG(dbgs() << "Split node operand: ";
968 N->dump(&DAG);
969 dbgs() << "\n");
970 SDValue Res = SDValue();
971
972 if (Res.getNode() == 0) {
973 switch (N->getOpcode()) {
974 default:
975 #ifndef NDEBUG
976 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
977 N->dump(&DAG);
978 dbgs() << "\n";
979 #endif
980 llvm_unreachable("Do not know how to split this operator's operand!");
981 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
982 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
983 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
984 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
985 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
986 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
987 case ISD::STORE:
988 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
989 break;
990
991 case ISD::CTTZ:
992 case ISD::CTLZ:
993 case ISD::CTPOP:
994 case ISD::FP_EXTEND:
995 case ISD::FP_TO_SINT:
996 case ISD::FP_TO_UINT:
997 case ISD::SINT_TO_FP:
998 case ISD::UINT_TO_FP:
999 case ISD::FTRUNC:
1000 case ISD::TRUNCATE:
1001 case ISD::SIGN_EXTEND:
1002 case ISD::ZERO_EXTEND:
1003 case ISD::ANY_EXTEND:
1004 Res = SplitVecOp_UnaryOp(N);
1005 break;
1006 }
1007 }
1008
1009 // If the result is null, the sub-method took care of registering results etc.
1010 if (!Res.getNode()) return false;
1011
1012 // If the result is N, the sub-method updated N in place. Tell the legalizer
1013 // core about this.
1014 if (Res.getNode() == N)
1015 return true;
1016
1017 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1018 "Invalid operand expansion");
1019
1020 ReplaceValueWith(SDValue(N, 0), Res);
1021 return false;
1022 }
1023
SplitVecOp_UnaryOp(SDNode * N)1024 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1025 // The result has a legal vector type, but the input needs splitting.
1026 EVT ResVT = N->getValueType(0);
1027 SDValue Lo, Hi;
1028 DebugLoc dl = N->getDebugLoc();
1029 GetSplitVector(N->getOperand(0), Lo, Hi);
1030 EVT InVT = Lo.getValueType();
1031
1032 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1033 InVT.getVectorNumElements());
1034
1035 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1036 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1037
1038 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1039 }
1040
SplitVecOp_BITCAST(SDNode * N)1041 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1042 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1043 // end up being split all the way down to individual components. Convert the
1044 // split pieces into integers and reassemble.
1045 SDValue Lo, Hi;
1046 GetSplitVector(N->getOperand(0), Lo, Hi);
1047 Lo = BitConvertToInteger(Lo);
1048 Hi = BitConvertToInteger(Hi);
1049
1050 if (TLI.isBigEndian())
1051 std::swap(Lo, Hi);
1052
1053 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0),
1054 JoinIntegers(Lo, Hi));
1055 }
1056
SplitVecOp_EXTRACT_SUBVECTOR(SDNode * N)1057 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1058 // We know that the extracted result type is legal.
1059 EVT SubVT = N->getValueType(0);
1060 SDValue Idx = N->getOperand(1);
1061 DebugLoc dl = N->getDebugLoc();
1062 SDValue Lo, Hi;
1063 GetSplitVector(N->getOperand(0), Lo, Hi);
1064
1065 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1066 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1067
1068 if (IdxVal < LoElts) {
1069 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1070 "Extracted subvector crosses vector split!");
1071 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1072 } else {
1073 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1074 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1075 }
1076 }
1077
SplitVecOp_EXTRACT_VECTOR_ELT(SDNode * N)1078 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1079 SDValue Vec = N->getOperand(0);
1080 SDValue Idx = N->getOperand(1);
1081 EVT VecVT = Vec.getValueType();
1082
1083 if (isa<ConstantSDNode>(Idx)) {
1084 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1085 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1086
1087 SDValue Lo, Hi;
1088 GetSplitVector(Vec, Lo, Hi);
1089
1090 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1091
1092 if (IdxVal < LoElts)
1093 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1094 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1095 DAG.getConstant(IdxVal - LoElts,
1096 Idx.getValueType())), 0);
1097 }
1098
1099 // Store the vector to the stack.
1100 EVT EltVT = VecVT.getVectorElementType();
1101 DebugLoc dl = N->getDebugLoc();
1102 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1103 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1104 MachinePointerInfo(), false, false, 0);
1105
1106 // Load back the required element.
1107 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1108 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1109 MachinePointerInfo(), EltVT, false, false, 0);
1110 }
1111
SplitVecOp_STORE(StoreSDNode * N,unsigned OpNo)1112 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1113 assert(N->isUnindexed() && "Indexed store of vector?");
1114 assert(OpNo == 1 && "Can only split the stored value");
1115 DebugLoc DL = N->getDebugLoc();
1116
1117 bool isTruncating = N->isTruncatingStore();
1118 SDValue Ch = N->getChain();
1119 SDValue Ptr = N->getBasePtr();
1120 EVT MemoryVT = N->getMemoryVT();
1121 unsigned Alignment = N->getOriginalAlignment();
1122 bool isVol = N->isVolatile();
1123 bool isNT = N->isNonTemporal();
1124 SDValue Lo, Hi;
1125 GetSplitVector(N->getOperand(1), Lo, Hi);
1126
1127 EVT LoMemVT, HiMemVT;
1128 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1129
1130 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1131
1132 if (isTruncating)
1133 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1134 LoMemVT, isVol, isNT, Alignment);
1135 else
1136 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1137 isVol, isNT, Alignment);
1138
1139 // Increment the pointer to the other half.
1140 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1141 DAG.getIntPtrConstant(IncrementSize));
1142
1143 if (isTruncating)
1144 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1145 N->getPointerInfo().getWithOffset(IncrementSize),
1146 HiMemVT, isVol, isNT, Alignment);
1147 else
1148 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1149 N->getPointerInfo().getWithOffset(IncrementSize),
1150 isVol, isNT, Alignment);
1151
1152 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1153 }
1154
SplitVecOp_CONCAT_VECTORS(SDNode * N)1155 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1156 DebugLoc DL = N->getDebugLoc();
1157
1158 // The input operands all must have the same type, and we know the result the
1159 // result type is valid. Convert this to a buildvector which extracts all the
1160 // input elements.
1161 // TODO: If the input elements are power-two vectors, we could convert this to
1162 // a new CONCAT_VECTORS node with elements that are half-wide.
1163 SmallVector<SDValue, 32> Elts;
1164 EVT EltVT = N->getValueType(0).getVectorElementType();
1165 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1166 SDValue Op = N->getOperand(op);
1167 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1168 i != e; ++i) {
1169 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1170 Op, DAG.getIntPtrConstant(i)));
1171
1172 }
1173 }
1174
1175 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0),
1176 &Elts[0], Elts.size());
1177 }
1178
SplitVecOp_VSETCC(SDNode * N)1179 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1180 assert(N->getValueType(0).isVector() &&
1181 N->getOperand(0).getValueType().isVector() &&
1182 "Operand types must be vectors");
1183 // The result has a legal vector type, but the input needs splitting.
1184 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1185 DebugLoc DL = N->getDebugLoc();
1186 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1187 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1188 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1189 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1190 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1191
1192 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1193 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1194 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1195 return PromoteTargetBoolean(Con, N->getValueType(0));
1196 }
1197
1198
SplitVecOp_FP_ROUND(SDNode * N)1199 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1200 // The result has a legal vector type, but the input needs splitting.
1201 EVT ResVT = N->getValueType(0);
1202 SDValue Lo, Hi;
1203 DebugLoc DL = N->getDebugLoc();
1204 GetSplitVector(N->getOperand(0), Lo, Hi);
1205 EVT InVT = Lo.getValueType();
1206
1207 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1208 InVT.getVectorNumElements());
1209
1210 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1211 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1212
1213 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1214 }
1215
1216
1217
1218 //===----------------------------------------------------------------------===//
1219 // Result Vector Widening
1220 //===----------------------------------------------------------------------===//
1221
WidenVectorResult(SDNode * N,unsigned ResNo)1222 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1223 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1224 N->dump(&DAG);
1225 dbgs() << "\n");
1226
1227 // See if the target wants to custom widen this node.
1228 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1229 return;
1230
1231 SDValue Res = SDValue();
1232 switch (N->getOpcode()) {
1233 default:
1234 #ifndef NDEBUG
1235 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1236 N->dump(&DAG);
1237 dbgs() << "\n";
1238 #endif
1239 llvm_unreachable("Do not know how to widen the result of this operator!");
1240
1241 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1242 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1243 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1244 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1245 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1246 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1247 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1248 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1249 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1250 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1251 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1252 case ISD::VSELECT:
1253 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1254 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1255 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1256 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1257 case ISD::VECTOR_SHUFFLE:
1258 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1259 break;
1260 case ISD::ADD:
1261 case ISD::AND:
1262 case ISD::BSWAP:
1263 case ISD::FADD:
1264 case ISD::FCOPYSIGN:
1265 case ISD::FDIV:
1266 case ISD::FMUL:
1267 case ISD::FPOW:
1268 case ISD::FREM:
1269 case ISD::FSUB:
1270 case ISD::MUL:
1271 case ISD::MULHS:
1272 case ISD::MULHU:
1273 case ISD::OR:
1274 case ISD::SDIV:
1275 case ISD::SREM:
1276 case ISD::UDIV:
1277 case ISD::UREM:
1278 case ISD::SUB:
1279 case ISD::XOR:
1280 Res = WidenVecRes_Binary(N);
1281 break;
1282
1283 case ISD::FPOWI:
1284 Res = WidenVecRes_POWI(N);
1285 break;
1286
1287 case ISD::SHL:
1288 case ISD::SRA:
1289 case ISD::SRL:
1290 Res = WidenVecRes_Shift(N);
1291 break;
1292
1293 case ISD::ANY_EXTEND:
1294 case ISD::FP_EXTEND:
1295 case ISD::FP_ROUND:
1296 case ISD::FP_TO_SINT:
1297 case ISD::FP_TO_UINT:
1298 case ISD::SIGN_EXTEND:
1299 case ISD::SINT_TO_FP:
1300 case ISD::TRUNCATE:
1301 case ISD::UINT_TO_FP:
1302 case ISD::ZERO_EXTEND:
1303 Res = WidenVecRes_Convert(N);
1304 break;
1305
1306 case ISD::CTLZ:
1307 case ISD::CTPOP:
1308 case ISD::CTTZ:
1309 case ISD::FABS:
1310 case ISD::FCEIL:
1311 case ISD::FCOS:
1312 case ISD::FEXP:
1313 case ISD::FEXP2:
1314 case ISD::FFLOOR:
1315 case ISD::FLOG:
1316 case ISD::FLOG10:
1317 case ISD::FLOG2:
1318 case ISD::FNEARBYINT:
1319 case ISD::FNEG:
1320 case ISD::FRINT:
1321 case ISD::FSIN:
1322 case ISD::FSQRT:
1323 case ISD::FTRUNC:
1324 Res = WidenVecRes_Unary(N);
1325 break;
1326 }
1327
1328 // If Res is null, the sub-method took care of registering the result.
1329 if (Res.getNode())
1330 SetWidenedVector(SDValue(N, ResNo), Res);
1331 }
1332
WidenVecRes_Binary(SDNode * N)1333 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1334 // Binary op widening.
1335 unsigned Opcode = N->getOpcode();
1336 DebugLoc dl = N->getDebugLoc();
1337 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1338 EVT WidenEltVT = WidenVT.getVectorElementType();
1339 EVT VT = WidenVT;
1340 unsigned NumElts = VT.getVectorNumElements();
1341 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1342 NumElts = NumElts / 2;
1343 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1344 }
1345
1346 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1347 // Operation doesn't trap so just widen as normal.
1348 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1349 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1350 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1351 }
1352
1353 // No legal vector version so unroll the vector operation and then widen.
1354 if (NumElts == 1)
1355 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
1356
1357 // Since the operation can trap, apply operation on the original vector.
1358 EVT MaxVT = VT;
1359 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1360 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1361 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
1362
1363 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
1364 unsigned ConcatEnd = 0; // Current ConcatOps index.
1365 int Idx = 0; // Current Idx into input vectors.
1366
1367 // NumElts := greatest legal vector size (at most WidenVT)
1368 // while (orig. vector has unhandled elements) {
1369 // take munches of size NumElts from the beginning and add to ConcatOps
1370 // NumElts := next smaller supported vector size or 1
1371 // }
1372 while (CurNumElts != 0) {
1373 while (CurNumElts >= NumElts) {
1374 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1375 DAG.getIntPtrConstant(Idx));
1376 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1377 DAG.getIntPtrConstant(Idx));
1378 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1379 Idx += NumElts;
1380 CurNumElts -= NumElts;
1381 }
1382 do {
1383 NumElts = NumElts / 2;
1384 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1385 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
1386
1387 if (NumElts == 1) {
1388 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
1389 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1390 InOp1, DAG.getIntPtrConstant(Idx));
1391 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1392 InOp2, DAG.getIntPtrConstant(Idx));
1393 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
1394 EOp1, EOp2);
1395 }
1396 CurNumElts = 0;
1397 }
1398 }
1399
1400 // Check to see if we have a single operation with the widen type.
1401 if (ConcatEnd == 1) {
1402 VT = ConcatOps[0].getValueType();
1403 if (VT == WidenVT)
1404 return ConcatOps[0];
1405 }
1406
1407 // while (Some element of ConcatOps is not of type MaxVT) {
1408 // From the end of ConcatOps, collect elements of the same type and put
1409 // them into an op of the next larger supported type
1410 // }
1411 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
1412 Idx = ConcatEnd - 1;
1413 VT = ConcatOps[Idx--].getValueType();
1414 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
1415 Idx--;
1416
1417 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
1418 EVT NextVT;
1419 do {
1420 NextSize *= 2;
1421 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
1422 } while (!TLI.isTypeLegal(NextVT));
1423
1424 if (!VT.isVector()) {
1425 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
1426 SDValue VecOp = DAG.getUNDEF(NextVT);
1427 unsigned NumToInsert = ConcatEnd - Idx - 1;
1428 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1429 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1430 ConcatOps[OpIdx], DAG.getIntPtrConstant(i));
1431 }
1432 ConcatOps[Idx+1] = VecOp;
1433 ConcatEnd = Idx + 2;
1434 } else {
1435 // Vector type, create a CONCAT_VECTORS of type NextVT
1436 SDValue undefVec = DAG.getUNDEF(VT);
1437 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
1438 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
1439 unsigned RealVals = ConcatEnd - Idx - 1;
1440 unsigned SubConcatEnd = 0;
1441 unsigned SubConcatIdx = Idx + 1;
1442 while (SubConcatEnd < RealVals)
1443 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
1444 while (SubConcatEnd < OpsToConcat)
1445 SubConcatOps[SubConcatEnd++] = undefVec;
1446 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1447 NextVT, &SubConcatOps[0],
1448 OpsToConcat);
1449 ConcatEnd = SubConcatIdx + 1;
1450 }
1451 }
1452
1453 // Check to see if we have a single operation with the widen type.
1454 if (ConcatEnd == 1) {
1455 VT = ConcatOps[0].getValueType();
1456 if (VT == WidenVT)
1457 return ConcatOps[0];
1458 }
1459
1460 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
1461 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
1462 if (NumOps != ConcatEnd ) {
1463 SDValue UndefVal = DAG.getUNDEF(MaxVT);
1464 for (unsigned j = ConcatEnd; j < NumOps; ++j)
1465 ConcatOps[j] = UndefVal;
1466 }
1467 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps);
1468 }
1469
WidenVecRes_Convert(SDNode * N)1470 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1471 SDValue InOp = N->getOperand(0);
1472 DebugLoc DL = N->getDebugLoc();
1473
1474 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1475 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1476
1477 EVT InVT = InOp.getValueType();
1478 EVT InEltVT = InVT.getVectorElementType();
1479 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1480
1481 unsigned Opcode = N->getOpcode();
1482 unsigned InVTNumElts = InVT.getVectorNumElements();
1483
1484 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1485 InOp = GetWidenedVector(N->getOperand(0));
1486 InVT = InOp.getValueType();
1487 InVTNumElts = InVT.getVectorNumElements();
1488 if (InVTNumElts == WidenNumElts) {
1489 if (N->getNumOperands() == 1)
1490 return DAG.getNode(Opcode, DL, WidenVT, InOp);
1491 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
1492 }
1493 }
1494
1495 if (TLI.isTypeLegal(InWidenVT)) {
1496 // Because the result and the input are different vector types, widening
1497 // the result could create a legal type but widening the input might make
1498 // it an illegal type that might lead to repeatedly splitting the input
1499 // and then widening it. To avoid this, we widen the input only if
1500 // it results in a legal type.
1501 if (WidenNumElts % InVTNumElts == 0) {
1502 // Widen the input and call convert on the widened input vector.
1503 unsigned NumConcat = WidenNumElts/InVTNumElts;
1504 SmallVector<SDValue, 16> Ops(NumConcat);
1505 Ops[0] = InOp;
1506 SDValue UndefVal = DAG.getUNDEF(InVT);
1507 for (unsigned i = 1; i != NumConcat; ++i)
1508 Ops[i] = UndefVal;
1509 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT,
1510 &Ops[0], NumConcat);
1511 if (N->getNumOperands() == 1)
1512 return DAG.getNode(Opcode, DL, WidenVT, InVec);
1513 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
1514 }
1515
1516 if (InVTNumElts % WidenNumElts == 0) {
1517 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
1518 InOp, DAG.getIntPtrConstant(0));
1519 // Extract the input and convert the shorten input vector.
1520 if (N->getNumOperands() == 1)
1521 return DAG.getNode(Opcode, DL, WidenVT, InVal);
1522 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
1523 }
1524 }
1525
1526 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1527 SmallVector<SDValue, 16> Ops(WidenNumElts);
1528 EVT EltVT = WidenVT.getVectorElementType();
1529 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1530 unsigned i;
1531 for (i=0; i < MinElts; ++i) {
1532 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
1533 DAG.getIntPtrConstant(i));
1534 if (N->getNumOperands() == 1)
1535 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
1536 else
1537 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
1538 }
1539
1540 SDValue UndefVal = DAG.getUNDEF(EltVT);
1541 for (; i < WidenNumElts; ++i)
1542 Ops[i] = UndefVal;
1543
1544 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts);
1545 }
1546
WidenVecRes_POWI(SDNode * N)1547 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
1548 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1549 SDValue InOp = GetWidenedVector(N->getOperand(0));
1550 SDValue ShOp = N->getOperand(1);
1551 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1552 }
1553
WidenVecRes_Shift(SDNode * N)1554 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1555 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1556 SDValue InOp = GetWidenedVector(N->getOperand(0));
1557 SDValue ShOp = N->getOperand(1);
1558
1559 EVT ShVT = ShOp.getValueType();
1560 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
1561 ShOp = GetWidenedVector(ShOp);
1562 ShVT = ShOp.getValueType();
1563 }
1564 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
1565 ShVT.getVectorElementType(),
1566 WidenVT.getVectorNumElements());
1567 if (ShVT != ShWidenVT)
1568 ShOp = ModifyToType(ShOp, ShWidenVT);
1569
1570 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1571 }
1572
WidenVecRes_Unary(SDNode * N)1573 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1574 // Unary op widening.
1575 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1576 SDValue InOp = GetWidenedVector(N->getOperand(0));
1577 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1578 }
1579
WidenVecRes_InregOp(SDNode * N)1580 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
1581 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1582 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
1583 cast<VTSDNode>(N->getOperand(1))->getVT()
1584 .getVectorElementType(),
1585 WidenVT.getVectorNumElements());
1586 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
1587 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
1588 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
1589 }
1590
WidenVecRes_MERGE_VALUES(SDNode * N,unsigned ResNo)1591 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
1592 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
1593 return GetWidenedVector(WidenVec);
1594 }
1595
WidenVecRes_BITCAST(SDNode * N)1596 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
1597 SDValue InOp = N->getOperand(0);
1598 EVT InVT = InOp.getValueType();
1599 EVT VT = N->getValueType(0);
1600 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1601 DebugLoc dl = N->getDebugLoc();
1602
1603 switch (getTypeAction(InVT)) {
1604 case TargetLowering::TypeLegal:
1605 break;
1606 case TargetLowering::TypePromoteInteger:
1607 // If the incoming type is a vector that is being promoted, then
1608 // we know that the elements are arranged differently and that we
1609 // must perform the conversion using a stack slot.
1610 if (InVT.isVector())
1611 break;
1612
1613 // If the InOp is promoted to the same size, convert it. Otherwise,
1614 // fall out of the switch and widen the promoted input.
1615 InOp = GetPromotedInteger(InOp);
1616 InVT = InOp.getValueType();
1617 if (WidenVT.bitsEq(InVT))
1618 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1619 break;
1620 case TargetLowering::TypeSoftenFloat:
1621 case TargetLowering::TypeExpandInteger:
1622 case TargetLowering::TypeExpandFloat:
1623 case TargetLowering::TypeScalarizeVector:
1624 case TargetLowering::TypeSplitVector:
1625 break;
1626 case TargetLowering::TypeWidenVector:
1627 // If the InOp is widened to the same size, convert it. Otherwise, fall
1628 // out of the switch and widen the widened input.
1629 InOp = GetWidenedVector(InOp);
1630 InVT = InOp.getValueType();
1631 if (WidenVT.bitsEq(InVT))
1632 // The input widens to the same size. Convert to the widen value.
1633 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1634 break;
1635 }
1636
1637 unsigned WidenSize = WidenVT.getSizeInBits();
1638 unsigned InSize = InVT.getSizeInBits();
1639 // x86mmx is not an acceptable vector element type, so don't try.
1640 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
1641 // Determine new input vector type. The new input vector type will use
1642 // the same element type (if its a vector) or use the input type as a
1643 // vector. It is the same size as the type to widen to.
1644 EVT NewInVT;
1645 unsigned NewNumElts = WidenSize / InSize;
1646 if (InVT.isVector()) {
1647 EVT InEltVT = InVT.getVectorElementType();
1648 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
1649 WidenSize / InEltVT.getSizeInBits());
1650 } else {
1651 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
1652 }
1653
1654 if (TLI.isTypeLegal(NewInVT)) {
1655 // Because the result and the input are different vector types, widening
1656 // the result could create a legal type but widening the input might make
1657 // it an illegal type that might lead to repeatedly splitting the input
1658 // and then widening it. To avoid this, we widen the input only if
1659 // it results in a legal type.
1660 SmallVector<SDValue, 16> Ops(NewNumElts);
1661 SDValue UndefVal = DAG.getUNDEF(InVT);
1662 Ops[0] = InOp;
1663 for (unsigned i = 1; i < NewNumElts; ++i)
1664 Ops[i] = UndefVal;
1665
1666 SDValue NewVec;
1667 if (InVT.isVector())
1668 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1669 NewInVT, &Ops[0], NewNumElts);
1670 else
1671 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1672 NewInVT, &Ops[0], NewNumElts);
1673 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
1674 }
1675 }
1676
1677 return CreateStackStoreLoad(InOp, WidenVT);
1678 }
1679
WidenVecRes_BUILD_VECTOR(SDNode * N)1680 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1681 DebugLoc dl = N->getDebugLoc();
1682 // Build a vector with undefined for the new nodes.
1683 EVT VT = N->getValueType(0);
1684 EVT EltVT = VT.getVectorElementType();
1685 unsigned NumElts = VT.getVectorNumElements();
1686
1687 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1688 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1689
1690 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1691 NewOps.reserve(WidenNumElts);
1692 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1693 NewOps.push_back(DAG.getUNDEF(EltVT));
1694
1695 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1696 }
1697
WidenVecRes_CONCAT_VECTORS(SDNode * N)1698 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1699 EVT InVT = N->getOperand(0).getValueType();
1700 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1701 DebugLoc dl = N->getDebugLoc();
1702 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1703 unsigned NumInElts = InVT.getVectorNumElements();
1704 unsigned NumOperands = N->getNumOperands();
1705
1706 bool InputWidened = false; // Indicates we need to widen the input.
1707 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
1708 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1709 // Add undef vectors to widen to correct length.
1710 unsigned NumConcat = WidenVT.getVectorNumElements() /
1711 InVT.getVectorNumElements();
1712 SDValue UndefVal = DAG.getUNDEF(InVT);
1713 SmallVector<SDValue, 16> Ops(NumConcat);
1714 for (unsigned i=0; i < NumOperands; ++i)
1715 Ops[i] = N->getOperand(i);
1716 for (unsigned i = NumOperands; i != NumConcat; ++i)
1717 Ops[i] = UndefVal;
1718 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1719 }
1720 } else {
1721 InputWidened = true;
1722 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
1723 // The inputs and the result are widen to the same value.
1724 unsigned i;
1725 for (i=1; i < NumOperands; ++i)
1726 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1727 break;
1728
1729 if (i == NumOperands)
1730 // Everything but the first operand is an UNDEF so just return the
1731 // widened first operand.
1732 return GetWidenedVector(N->getOperand(0));
1733
1734 if (NumOperands == 2) {
1735 // Replace concat of two operands with a shuffle.
1736 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
1737 for (unsigned i = 0; i < NumInElts; ++i) {
1738 MaskOps[i] = i;
1739 MaskOps[i + NumInElts] = i + WidenNumElts;
1740 }
1741 return DAG.getVectorShuffle(WidenVT, dl,
1742 GetWidenedVector(N->getOperand(0)),
1743 GetWidenedVector(N->getOperand(1)),
1744 &MaskOps[0]);
1745 }
1746 }
1747 }
1748
1749 // Fall back to use extracts and build vector.
1750 EVT EltVT = WidenVT.getVectorElementType();
1751 SmallVector<SDValue, 16> Ops(WidenNumElts);
1752 unsigned Idx = 0;
1753 for (unsigned i=0; i < NumOperands; ++i) {
1754 SDValue InOp = N->getOperand(i);
1755 if (InputWidened)
1756 InOp = GetWidenedVector(InOp);
1757 for (unsigned j=0; j < NumInElts; ++j)
1758 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1759 DAG.getIntPtrConstant(j));
1760 }
1761 SDValue UndefVal = DAG.getUNDEF(EltVT);
1762 for (; Idx < WidenNumElts; ++Idx)
1763 Ops[Idx] = UndefVal;
1764 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1765 }
1766
WidenVecRes_CONVERT_RNDSAT(SDNode * N)1767 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1768 DebugLoc dl = N->getDebugLoc();
1769 SDValue InOp = N->getOperand(0);
1770 SDValue RndOp = N->getOperand(3);
1771 SDValue SatOp = N->getOperand(4);
1772
1773 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1774 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1775
1776 EVT InVT = InOp.getValueType();
1777 EVT InEltVT = InVT.getVectorElementType();
1778 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1779
1780 SDValue DTyOp = DAG.getValueType(WidenVT);
1781 SDValue STyOp = DAG.getValueType(InWidenVT);
1782 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1783
1784 unsigned InVTNumElts = InVT.getVectorNumElements();
1785 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1786 InOp = GetWidenedVector(InOp);
1787 InVT = InOp.getValueType();
1788 InVTNumElts = InVT.getVectorNumElements();
1789 if (InVTNumElts == WidenNumElts)
1790 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1791 SatOp, CvtCode);
1792 }
1793
1794 if (TLI.isTypeLegal(InWidenVT)) {
1795 // Because the result and the input are different vector types, widening
1796 // the result could create a legal type but widening the input might make
1797 // it an illegal type that might lead to repeatedly splitting the input
1798 // and then widening it. To avoid this, we widen the input only if
1799 // it results in a legal type.
1800 if (WidenNumElts % InVTNumElts == 0) {
1801 // Widen the input and call convert on the widened input vector.
1802 unsigned NumConcat = WidenNumElts/InVTNumElts;
1803 SmallVector<SDValue, 16> Ops(NumConcat);
1804 Ops[0] = InOp;
1805 SDValue UndefVal = DAG.getUNDEF(InVT);
1806 for (unsigned i = 1; i != NumConcat; ++i)
1807 Ops[i] = UndefVal;
1808
1809 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1810 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1811 SatOp, CvtCode);
1812 }
1813
1814 if (InVTNumElts % WidenNumElts == 0) {
1815 // Extract the input and convert the shorten input vector.
1816 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1817 DAG.getIntPtrConstant(0));
1818 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1819 SatOp, CvtCode);
1820 }
1821 }
1822
1823 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1824 SmallVector<SDValue, 16> Ops(WidenNumElts);
1825 EVT EltVT = WidenVT.getVectorElementType();
1826 DTyOp = DAG.getValueType(EltVT);
1827 STyOp = DAG.getValueType(InEltVT);
1828
1829 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1830 unsigned i;
1831 for (i=0; i < MinElts; ++i) {
1832 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1833 DAG.getIntPtrConstant(i));
1834 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
1835 SatOp, CvtCode);
1836 }
1837
1838 SDValue UndefVal = DAG.getUNDEF(EltVT);
1839 for (; i < WidenNumElts; ++i)
1840 Ops[i] = UndefVal;
1841
1842 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1843 }
1844
WidenVecRes_EXTRACT_SUBVECTOR(SDNode * N)1845 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1846 EVT VT = N->getValueType(0);
1847 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1848 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1849 SDValue InOp = N->getOperand(0);
1850 SDValue Idx = N->getOperand(1);
1851 DebugLoc dl = N->getDebugLoc();
1852
1853 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
1854 InOp = GetWidenedVector(InOp);
1855
1856 EVT InVT = InOp.getValueType();
1857
1858 // Check if we can just return the input vector after widening.
1859 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1860 if (IdxVal == 0 && InVT == WidenVT)
1861 return InOp;
1862
1863 // Check if we can extract from the vector.
1864 unsigned InNumElts = InVT.getVectorNumElements();
1865 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1866 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1867
1868 // We could try widening the input to the right length but for now, extract
1869 // the original elements, fill the rest with undefs and build a vector.
1870 SmallVector<SDValue, 16> Ops(WidenNumElts);
1871 EVT EltVT = VT.getVectorElementType();
1872 unsigned NumElts = VT.getVectorNumElements();
1873 unsigned i;
1874 for (i=0; i < NumElts; ++i)
1875 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1876 DAG.getIntPtrConstant(IdxVal+i));
1877
1878 SDValue UndefVal = DAG.getUNDEF(EltVT);
1879 for (; i < WidenNumElts; ++i)
1880 Ops[i] = UndefVal;
1881 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1882 }
1883
WidenVecRes_INSERT_VECTOR_ELT(SDNode * N)1884 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1885 SDValue InOp = GetWidenedVector(N->getOperand(0));
1886 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1887 InOp.getValueType(), InOp,
1888 N->getOperand(1), N->getOperand(2));
1889 }
1890
WidenVecRes_LOAD(SDNode * N)1891 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
1892 LoadSDNode *LD = cast<LoadSDNode>(N);
1893 ISD::LoadExtType ExtType = LD->getExtensionType();
1894
1895 SDValue Result;
1896 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
1897 if (ExtType != ISD::NON_EXTLOAD)
1898 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
1899 else
1900 Result = GenWidenVectorLoads(LdChain, LD);
1901
1902 // If we generate a single load, we can use that for the chain. Otherwise,
1903 // build a factor node to remember the multiple loads are independent and
1904 // chain to that.
1905 SDValue NewChain;
1906 if (LdChain.size() == 1)
1907 NewChain = LdChain[0];
1908 else
1909 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other,
1910 &LdChain[0], LdChain.size());
1911
1912 // Modified the chain - switch anything that used the old chain to use
1913 // the new one.
1914 ReplaceValueWith(SDValue(N, 1), NewChain);
1915
1916 return Result;
1917 }
1918
WidenVecRes_SCALAR_TO_VECTOR(SDNode * N)1919 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1920 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1921 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1922 WidenVT, N->getOperand(0));
1923 }
1924
WidenVecRes_SELECT(SDNode * N)1925 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1926 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1927 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1928
1929 SDValue Cond1 = N->getOperand(0);
1930 EVT CondVT = Cond1.getValueType();
1931 if (CondVT.isVector()) {
1932 EVT CondEltVT = CondVT.getVectorElementType();
1933 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
1934 CondEltVT, WidenNumElts);
1935 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
1936 Cond1 = GetWidenedVector(Cond1);
1937
1938 if (Cond1.getValueType() != CondWidenVT)
1939 Cond1 = ModifyToType(Cond1, CondWidenVT);
1940 }
1941
1942 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
1943 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
1944 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
1945 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
1946 WidenVT, Cond1, InOp1, InOp2);
1947 }
1948
WidenVecRes_SELECT_CC(SDNode * N)1949 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
1950 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
1951 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
1952 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
1953 InOp1.getValueType(), N->getOperand(0),
1954 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
1955 }
1956
WidenVecRes_SETCC(SDNode * N)1957 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
1958 assert(N->getValueType(0).isVector() ==
1959 N->getOperand(0).getValueType().isVector() &&
1960 "Scalar/Vector type mismatch");
1961 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
1962
1963 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1964 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1965 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1966 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT,
1967 InOp1, InOp2, N->getOperand(2));
1968 }
1969
WidenVecRes_UNDEF(SDNode * N)1970 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1971 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1972 return DAG.getUNDEF(WidenVT);
1973 }
1974
WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode * N)1975 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
1976 EVT VT = N->getValueType(0);
1977 DebugLoc dl = N->getDebugLoc();
1978
1979 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1980 unsigned NumElts = VT.getVectorNumElements();
1981 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1982
1983 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1984 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1985
1986 // Adjust mask based on new input vector length.
1987 SmallVector<int, 16> NewMask;
1988 for (unsigned i = 0; i != NumElts; ++i) {
1989 int Idx = N->getMaskElt(i);
1990 if (Idx < (int)NumElts)
1991 NewMask.push_back(Idx);
1992 else
1993 NewMask.push_back(Idx - NumElts + WidenNumElts);
1994 }
1995 for (unsigned i = NumElts; i != WidenNumElts; ++i)
1996 NewMask.push_back(-1);
1997 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
1998 }
1999
WidenVecRes_VSETCC(SDNode * N)2000 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
2001 assert(N->getValueType(0).isVector() &&
2002 N->getOperand(0).getValueType().isVector() &&
2003 "Operands must be vectors");
2004 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2005 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2006
2007 SDValue InOp1 = N->getOperand(0);
2008 EVT InVT = InOp1.getValueType();
2009 assert(InVT.isVector() && "can not widen non vector type");
2010 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
2011 InVT.getVectorElementType(), WidenNumElts);
2012 InOp1 = GetWidenedVector(InOp1);
2013 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2014
2015 // Assume that the input and output will be widen appropriately. If not,
2016 // we will have to unroll it at some point.
2017 assert(InOp1.getValueType() == WidenInVT &&
2018 InOp2.getValueType() == WidenInVT &&
2019 "Input not widened to expected type!");
2020 (void)WidenInVT;
2021 return DAG.getNode(ISD::SETCC, N->getDebugLoc(),
2022 WidenVT, InOp1, InOp2, N->getOperand(2));
2023 }
2024
2025
2026 //===----------------------------------------------------------------------===//
2027 // Widen Vector Operand
2028 //===----------------------------------------------------------------------===//
WidenVectorOperand(SDNode * N,unsigned ResNo)2029 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
2030 DEBUG(dbgs() << "Widen node operand " << ResNo << ": ";
2031 N->dump(&DAG);
2032 dbgs() << "\n");
2033 SDValue Res = SDValue();
2034
2035 switch (N->getOpcode()) {
2036 default:
2037 #ifndef NDEBUG
2038 dbgs() << "WidenVectorOperand op #" << ResNo << ": ";
2039 N->dump(&DAG);
2040 dbgs() << "\n";
2041 #endif
2042 llvm_unreachable("Do not know how to widen this operator's operand!");
2043
2044 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2045 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2046 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2047 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2048 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2049 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2050
2051 case ISD::FP_EXTEND:
2052 case ISD::FP_TO_SINT:
2053 case ISD::FP_TO_UINT:
2054 case ISD::SINT_TO_FP:
2055 case ISD::UINT_TO_FP:
2056 case ISD::TRUNCATE:
2057 case ISD::SIGN_EXTEND:
2058 case ISD::ZERO_EXTEND:
2059 case ISD::ANY_EXTEND:
2060 Res = WidenVecOp_Convert(N);
2061 break;
2062 }
2063
2064 // If Res is null, the sub-method took care of registering the result.
2065 if (!Res.getNode()) return false;
2066
2067 // If the result is N, the sub-method updated N in place. Tell the legalizer
2068 // core about this.
2069 if (Res.getNode() == N)
2070 return true;
2071
2072
2073 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2074 "Invalid operand expansion");
2075
2076 ReplaceValueWith(SDValue(N, 0), Res);
2077 return false;
2078 }
2079
WidenVecOp_Convert(SDNode * N)2080 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2081 // Since the result is legal and the input is illegal, it is unlikely
2082 // that we can fix the input to a legal type so unroll the convert
2083 // into some scalar code and create a nasty build vector.
2084 EVT VT = N->getValueType(0);
2085 EVT EltVT = VT.getVectorElementType();
2086 DebugLoc dl = N->getDebugLoc();
2087 unsigned NumElts = VT.getVectorNumElements();
2088 SDValue InOp = N->getOperand(0);
2089 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2090 InOp = GetWidenedVector(InOp);
2091 EVT InVT = InOp.getValueType();
2092 EVT InEltVT = InVT.getVectorElementType();
2093
2094 unsigned Opcode = N->getOpcode();
2095 SmallVector<SDValue, 16> Ops(NumElts);
2096 for (unsigned i=0; i < NumElts; ++i)
2097 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2098 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2099 DAG.getIntPtrConstant(i)));
2100
2101 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2102 }
2103
WidenVecOp_BITCAST(SDNode * N)2104 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2105 EVT VT = N->getValueType(0);
2106 SDValue InOp = GetWidenedVector(N->getOperand(0));
2107 EVT InWidenVT = InOp.getValueType();
2108 DebugLoc dl = N->getDebugLoc();
2109
2110 // Check if we can convert between two legal vector types and extract.
2111 unsigned InWidenSize = InWidenVT.getSizeInBits();
2112 unsigned Size = VT.getSizeInBits();
2113 // x86mmx is not an acceptable vector element type, so don't try.
2114 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2115 unsigned NewNumElts = InWidenSize / Size;
2116 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2117 if (TLI.isTypeLegal(NewVT)) {
2118 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2119 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2120 DAG.getIntPtrConstant(0));
2121 }
2122 }
2123
2124 return CreateStackStoreLoad(InOp, VT);
2125 }
2126
WidenVecOp_CONCAT_VECTORS(SDNode * N)2127 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2128 // If the input vector is not legal, it is likely that we will not find a
2129 // legal vector of the same size. Replace the concatenate vector with a
2130 // nasty build vector.
2131 EVT VT = N->getValueType(0);
2132 EVT EltVT = VT.getVectorElementType();
2133 DebugLoc dl = N->getDebugLoc();
2134 unsigned NumElts = VT.getVectorNumElements();
2135 SmallVector<SDValue, 16> Ops(NumElts);
2136
2137 EVT InVT = N->getOperand(0).getValueType();
2138 unsigned NumInElts = InVT.getVectorNumElements();
2139
2140 unsigned Idx = 0;
2141 unsigned NumOperands = N->getNumOperands();
2142 for (unsigned i=0; i < NumOperands; ++i) {
2143 SDValue InOp = N->getOperand(i);
2144 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2145 InOp = GetWidenedVector(InOp);
2146 for (unsigned j=0; j < NumInElts; ++j)
2147 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2148 DAG.getIntPtrConstant(j));
2149 }
2150 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2151 }
2152
WidenVecOp_EXTRACT_SUBVECTOR(SDNode * N)2153 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2154 SDValue InOp = GetWidenedVector(N->getOperand(0));
2155 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(),
2156 N->getValueType(0), InOp, N->getOperand(1));
2157 }
2158
WidenVecOp_EXTRACT_VECTOR_ELT(SDNode * N)2159 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2160 SDValue InOp = GetWidenedVector(N->getOperand(0));
2161 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
2162 N->getValueType(0), InOp, N->getOperand(1));
2163 }
2164
WidenVecOp_STORE(SDNode * N)2165 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2166 // We have to widen the value but we want only to store the original
2167 // vector type.
2168 StoreSDNode *ST = cast<StoreSDNode>(N);
2169
2170 SmallVector<SDValue, 16> StChain;
2171 if (ST->isTruncatingStore())
2172 GenWidenVectorTruncStores(StChain, ST);
2173 else
2174 GenWidenVectorStores(StChain, ST);
2175
2176 if (StChain.size() == 1)
2177 return StChain[0];
2178 else
2179 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(),
2180 MVT::Other,&StChain[0],StChain.size());
2181 }
2182
WidenVecOp_SETCC(SDNode * N)2183 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
2184 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
2185 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2186 DebugLoc dl = N->getDebugLoc();
2187
2188 // WARNING: In this code we widen the compare instruction with garbage.
2189 // This garbage may contain denormal floats which may be slow. Is this a real
2190 // concern ? Should we zero the unused lanes if this is a float compare ?
2191
2192 // Get a new SETCC node to compare the newly widened operands.
2193 // Only some of the compared elements are legal.
2194 EVT SVT = TLI.getSetCCResultType(InOp0.getValueType());
2195 SDValue WideSETCC = DAG.getNode(ISD::SETCC, N->getDebugLoc(),
2196 SVT, InOp0, InOp1, N->getOperand(2));
2197
2198 // Extract the needed results from the result vector.
2199 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
2200 SVT.getVectorElementType(),
2201 N->getValueType(0).getVectorNumElements());
2202 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
2203 ResVT, WideSETCC, DAG.getIntPtrConstant(0));
2204
2205 return PromoteTargetBoolean(CC, N->getValueType(0));
2206 }
2207
2208
2209 //===----------------------------------------------------------------------===//
2210 // Vector Widening Utilities
2211 //===----------------------------------------------------------------------===//
2212
2213 // Utility function to find the type to chop up a widen vector for load/store
2214 // TLI: Target lowering used to determine legal types.
2215 // Width: Width left need to load/store.
2216 // WidenVT: The widen vector type to load to/store from
2217 // Align: If 0, don't allow use of a wider type
2218 // WidenEx: If Align is not 0, the amount additional we can load/store from.
2219
FindMemType(SelectionDAG & DAG,const TargetLowering & TLI,unsigned Width,EVT WidenVT,unsigned Align=0,unsigned WidenEx=0)2220 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
2221 unsigned Width, EVT WidenVT,
2222 unsigned Align = 0, unsigned WidenEx = 0) {
2223 EVT WidenEltVT = WidenVT.getVectorElementType();
2224 unsigned WidenWidth = WidenVT.getSizeInBits();
2225 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
2226 unsigned AlignInBits = Align*8;
2227
2228 // If we have one element to load/store, return it.
2229 EVT RetVT = WidenEltVT;
2230 if (Width == WidenEltWidth)
2231 return RetVT;
2232
2233 // See if there is larger legal integer than the element type to load/store
2234 unsigned VT;
2235 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
2236 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
2237 EVT MemVT((MVT::SimpleValueType) VT);
2238 unsigned MemVTWidth = MemVT.getSizeInBits();
2239 if (MemVT.getSizeInBits() <= WidenEltWidth)
2240 break;
2241 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
2242 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2243 (MemVTWidth <= Width ||
2244 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2245 RetVT = MemVT;
2246 break;
2247 }
2248 }
2249
2250 // See if there is a larger vector type to load/store that has the same vector
2251 // element type and is evenly divisible with the WidenVT.
2252 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
2253 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
2254 EVT MemVT = (MVT::SimpleValueType) VT;
2255 unsigned MemVTWidth = MemVT.getSizeInBits();
2256 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
2257 (WidenWidth % MemVTWidth) == 0 &&
2258 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2259 (MemVTWidth <= Width ||
2260 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2261 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2262 return MemVT;
2263 }
2264 }
2265
2266 return RetVT;
2267 }
2268
2269 // Builds a vector type from scalar loads
2270 // VecTy: Resulting Vector type
2271 // LDOps: Load operators to build a vector type
2272 // [Start,End) the list of loads to use.
BuildVectorFromScalar(SelectionDAG & DAG,EVT VecTy,SmallVector<SDValue,16> & LdOps,unsigned Start,unsigned End)2273 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
2274 SmallVector<SDValue, 16>& LdOps,
2275 unsigned Start, unsigned End) {
2276 DebugLoc dl = LdOps[Start].getDebugLoc();
2277 EVT LdTy = LdOps[Start].getValueType();
2278 unsigned Width = VecTy.getSizeInBits();
2279 unsigned NumElts = Width / LdTy.getSizeInBits();
2280 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2281
2282 unsigned Idx = 1;
2283 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2284
2285 for (unsigned i = Start + 1; i != End; ++i) {
2286 EVT NewLdTy = LdOps[i].getValueType();
2287 if (NewLdTy != LdTy) {
2288 NumElts = Width / NewLdTy.getSizeInBits();
2289 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2290 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2291 // Readjust position and vector position based on new load type
2292 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2293 LdTy = NewLdTy;
2294 }
2295 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2296 DAG.getIntPtrConstant(Idx++));
2297 }
2298 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2299 }
2300
GenWidenVectorLoads(SmallVector<SDValue,16> & LdChain,LoadSDNode * LD)2301 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain,
2302 LoadSDNode *LD) {
2303 // The strategy assumes that we can efficiently load powers of two widths.
2304 // The routines chops the vector into the largest vector loads with the same
2305 // element type or scalar loads and then recombines it to the widen vector
2306 // type.
2307 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2308 unsigned WidenWidth = WidenVT.getSizeInBits();
2309 EVT LdVT = LD->getMemoryVT();
2310 DebugLoc dl = LD->getDebugLoc();
2311 assert(LdVT.isVector() && WidenVT.isVector());
2312 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
2313
2314 // Load information
2315 SDValue Chain = LD->getChain();
2316 SDValue BasePtr = LD->getBasePtr();
2317 unsigned Align = LD->getAlignment();
2318 bool isVolatile = LD->isVolatile();
2319 bool isNonTemporal = LD->isNonTemporal();
2320 bool isInvariant = LD->isInvariant();
2321
2322 int LdWidth = LdVT.getSizeInBits();
2323 int WidthDiff = WidenWidth - LdWidth; // Difference
2324 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
2325
2326 // Find the vector type that can load from.
2327 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2328 int NewVTWidth = NewVT.getSizeInBits();
2329 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
2330 isVolatile, isNonTemporal, isInvariant, Align);
2331 LdChain.push_back(LdOp.getValue(1));
2332
2333 // Check if we can load the element with one instruction
2334 if (LdWidth <= NewVTWidth) {
2335 if (!NewVT.isVector()) {
2336 unsigned NumElts = WidenWidth / NewVTWidth;
2337 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2338 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2339 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
2340 }
2341 if (NewVT == WidenVT)
2342 return LdOp;
2343
2344 assert(WidenWidth % NewVTWidth == 0);
2345 unsigned NumConcat = WidenWidth / NewVTWidth;
2346 SmallVector<SDValue, 16> ConcatOps(NumConcat);
2347 SDValue UndefVal = DAG.getUNDEF(NewVT);
2348 ConcatOps[0] = LdOp;
2349 for (unsigned i = 1; i != NumConcat; ++i)
2350 ConcatOps[i] = UndefVal;
2351 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0],
2352 NumConcat);
2353 }
2354
2355 // Load vector by using multiple loads from largest vector to scalar
2356 SmallVector<SDValue, 16> LdOps;
2357 LdOps.push_back(LdOp);
2358
2359 LdWidth -= NewVTWidth;
2360 unsigned Offset = 0;
2361
2362 while (LdWidth > 0) {
2363 unsigned Increment = NewVTWidth / 8;
2364 Offset += Increment;
2365 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2366 DAG.getIntPtrConstant(Increment));
2367
2368 SDValue L;
2369 if (LdWidth < NewVTWidth) {
2370 // Our current type we are using is too large, find a better size
2371 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2372 NewVTWidth = NewVT.getSizeInBits();
2373 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2374 LD->getPointerInfo().getWithOffset(Offset),
2375 isVolatile,
2376 isNonTemporal, isInvariant,
2377 MinAlign(Align, Increment));
2378 LdChain.push_back(L.getValue(1));
2379 if (L->getValueType(0).isVector()) {
2380 SmallVector<SDValue, 16> Loads;
2381 Loads.push_back(L);
2382 unsigned size = L->getValueSizeInBits(0);
2383 while (size < LdOp->getValueSizeInBits(0)) {
2384 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
2385 size += L->getValueSizeInBits(0);
2386 }
2387 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0),
2388 &Loads[0], Loads.size());
2389 }
2390 } else {
2391 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2392 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
2393 isNonTemporal, isInvariant, MinAlign(Align, Increment));
2394 LdChain.push_back(L.getValue(1));
2395 }
2396
2397 LdOps.push_back(L);
2398
2399
2400 LdWidth -= NewVTWidth;
2401 }
2402
2403 // Build the vector from the loads operations
2404 unsigned End = LdOps.size();
2405 if (!LdOps[0].getValueType().isVector())
2406 // All the loads are scalar loads.
2407 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
2408
2409 // If the load contains vectors, build the vector using concat vector.
2410 // All of the vectors used to loads are power of 2 and the scalars load
2411 // can be combined to make a power of 2 vector.
2412 SmallVector<SDValue, 16> ConcatOps(End);
2413 int i = End - 1;
2414 int Idx = End;
2415 EVT LdTy = LdOps[i].getValueType();
2416 // First combine the scalar loads to a vector
2417 if (!LdTy.isVector()) {
2418 for (--i; i >= 0; --i) {
2419 LdTy = LdOps[i].getValueType();
2420 if (LdTy.isVector())
2421 break;
2422 }
2423 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
2424 }
2425 ConcatOps[--Idx] = LdOps[i];
2426 for (--i; i >= 0; --i) {
2427 EVT NewLdTy = LdOps[i].getValueType();
2428 if (NewLdTy != LdTy) {
2429 // Create a larger vector
2430 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
2431 &ConcatOps[Idx], End - Idx);
2432 Idx = End - 1;
2433 LdTy = NewLdTy;
2434 }
2435 ConcatOps[--Idx] = LdOps[i];
2436 }
2437
2438 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
2439 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2440 &ConcatOps[Idx], End - Idx);
2441
2442 // We need to fill the rest with undefs to build the vector
2443 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
2444 SmallVector<SDValue, 16> WidenOps(NumOps);
2445 SDValue UndefVal = DAG.getUNDEF(LdTy);
2446 {
2447 unsigned i = 0;
2448 for (; i != End-Idx; ++i)
2449 WidenOps[i] = ConcatOps[Idx+i];
2450 for (; i != NumOps; ++i)
2451 WidenOps[i] = UndefVal;
2452 }
2453 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps);
2454 }
2455
2456 SDValue
GenWidenVectorExtLoads(SmallVector<SDValue,16> & LdChain,LoadSDNode * LD,ISD::LoadExtType ExtType)2457 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain,
2458 LoadSDNode * LD,
2459 ISD::LoadExtType ExtType) {
2460 // For extension loads, it may not be more efficient to chop up the vector
2461 // and then extended it. Instead, we unroll the load and build a new vector.
2462 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2463 EVT LdVT = LD->getMemoryVT();
2464 DebugLoc dl = LD->getDebugLoc();
2465 assert(LdVT.isVector() && WidenVT.isVector());
2466
2467 // Load information
2468 SDValue Chain = LD->getChain();
2469 SDValue BasePtr = LD->getBasePtr();
2470 unsigned Align = LD->getAlignment();
2471 bool isVolatile = LD->isVolatile();
2472 bool isNonTemporal = LD->isNonTemporal();
2473
2474 EVT EltVT = WidenVT.getVectorElementType();
2475 EVT LdEltVT = LdVT.getVectorElementType();
2476 unsigned NumElts = LdVT.getVectorNumElements();
2477
2478 // Load each element and widen
2479 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2480 SmallVector<SDValue, 16> Ops(WidenNumElts);
2481 unsigned Increment = LdEltVT.getSizeInBits() / 8;
2482 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
2483 LD->getPointerInfo(),
2484 LdEltVT, isVolatile, isNonTemporal, Align);
2485 LdChain.push_back(Ops[0].getValue(1));
2486 unsigned i = 0, Offset = Increment;
2487 for (i=1; i < NumElts; ++i, Offset += Increment) {
2488 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2489 BasePtr, DAG.getIntPtrConstant(Offset));
2490 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
2491 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
2492 isVolatile, isNonTemporal, Align);
2493 LdChain.push_back(Ops[i].getValue(1));
2494 }
2495
2496 // Fill the rest with undefs
2497 SDValue UndefVal = DAG.getUNDEF(EltVT);
2498 for (; i != WidenNumElts; ++i)
2499 Ops[i] = UndefVal;
2500
2501 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
2502 }
2503
2504
GenWidenVectorStores(SmallVector<SDValue,16> & StChain,StoreSDNode * ST)2505 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2506 StoreSDNode *ST) {
2507 // The strategy assumes that we can efficiently store powers of two widths.
2508 // The routines chops the vector into the largest vector stores with the same
2509 // element type or scalar stores.
2510 SDValue Chain = ST->getChain();
2511 SDValue BasePtr = ST->getBasePtr();
2512 unsigned Align = ST->getAlignment();
2513 bool isVolatile = ST->isVolatile();
2514 bool isNonTemporal = ST->isNonTemporal();
2515 SDValue ValOp = GetWidenedVector(ST->getValue());
2516 DebugLoc dl = ST->getDebugLoc();
2517
2518 EVT StVT = ST->getMemoryVT();
2519 unsigned StWidth = StVT.getSizeInBits();
2520 EVT ValVT = ValOp.getValueType();
2521 unsigned ValWidth = ValVT.getSizeInBits();
2522 EVT ValEltVT = ValVT.getVectorElementType();
2523 unsigned ValEltWidth = ValEltVT.getSizeInBits();
2524 assert(StVT.getVectorElementType() == ValEltVT);
2525
2526 int Idx = 0; // current index to store
2527 unsigned Offset = 0; // offset from base to store
2528 while (StWidth != 0) {
2529 // Find the largest vector type we can store with
2530 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
2531 unsigned NewVTWidth = NewVT.getSizeInBits();
2532 unsigned Increment = NewVTWidth / 8;
2533 if (NewVT.isVector()) {
2534 unsigned NumVTElts = NewVT.getVectorNumElements();
2535 do {
2536 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
2537 DAG.getIntPtrConstant(Idx));
2538 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2539 ST->getPointerInfo().getWithOffset(Offset),
2540 isVolatile, isNonTemporal,
2541 MinAlign(Align, Offset)));
2542 StWidth -= NewVTWidth;
2543 Offset += Increment;
2544 Idx += NumVTElts;
2545 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2546 DAG.getIntPtrConstant(Increment));
2547 } while (StWidth != 0 && StWidth >= NewVTWidth);
2548 } else {
2549 // Cast the vector to the scalar type we can store
2550 unsigned NumElts = ValWidth / NewVTWidth;
2551 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2552 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
2553 // Readjust index position based on new vector type
2554 Idx = Idx * ValEltWidth / NewVTWidth;
2555 do {
2556 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
2557 DAG.getIntPtrConstant(Idx++));
2558 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2559 ST->getPointerInfo().getWithOffset(Offset),
2560 isVolatile, isNonTemporal,
2561 MinAlign(Align, Offset)));
2562 StWidth -= NewVTWidth;
2563 Offset += Increment;
2564 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2565 DAG.getIntPtrConstant(Increment));
2566 } while (StWidth != 0 && StWidth >= NewVTWidth);
2567 // Restore index back to be relative to the original widen element type
2568 Idx = Idx * NewVTWidth / ValEltWidth;
2569 }
2570 }
2571 }
2572
2573 void
GenWidenVectorTruncStores(SmallVector<SDValue,16> & StChain,StoreSDNode * ST)2574 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain,
2575 StoreSDNode *ST) {
2576 // For extension loads, it may not be more efficient to truncate the vector
2577 // and then store it. Instead, we extract each element and then store it.
2578 SDValue Chain = ST->getChain();
2579 SDValue BasePtr = ST->getBasePtr();
2580 unsigned Align = ST->getAlignment();
2581 bool isVolatile = ST->isVolatile();
2582 bool isNonTemporal = ST->isNonTemporal();
2583 SDValue ValOp = GetWidenedVector(ST->getValue());
2584 DebugLoc dl = ST->getDebugLoc();
2585
2586 EVT StVT = ST->getMemoryVT();
2587 EVT ValVT = ValOp.getValueType();
2588
2589 // It must be true that we the widen vector type is bigger than where
2590 // we need to store.
2591 assert(StVT.isVector() && ValOp.getValueType().isVector());
2592 assert(StVT.bitsLT(ValOp.getValueType()));
2593
2594 // For truncating stores, we can not play the tricks of chopping legal
2595 // vector types and bit cast it to the right type. Instead, we unroll
2596 // the store.
2597 EVT StEltVT = StVT.getVectorElementType();
2598 EVT ValEltVT = ValVT.getVectorElementType();
2599 unsigned Increment = ValEltVT.getSizeInBits() / 8;
2600 unsigned NumElts = StVT.getVectorNumElements();
2601 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2602 DAG.getIntPtrConstant(0));
2603 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
2604 ST->getPointerInfo(), StEltVT,
2605 isVolatile, isNonTemporal, Align));
2606 unsigned Offset = Increment;
2607 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
2608 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2609 BasePtr, DAG.getIntPtrConstant(Offset));
2610 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2611 DAG.getIntPtrConstant(0));
2612 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
2613 ST->getPointerInfo().getWithOffset(Offset),
2614 StEltVT, isVolatile, isNonTemporal,
2615 MinAlign(Align, Offset)));
2616 }
2617 }
2618
2619 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2620 /// input vector must have the same element type as NVT.
ModifyToType(SDValue InOp,EVT NVT)2621 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
2622 // Note that InOp might have been widened so it might already have
2623 // the right width or it might need be narrowed.
2624 EVT InVT = InOp.getValueType();
2625 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2626 "input and widen element type must match");
2627 DebugLoc dl = InOp.getDebugLoc();
2628
2629 // Check if InOp already has the right width.
2630 if (InVT == NVT)
2631 return InOp;
2632
2633 unsigned InNumElts = InVT.getVectorNumElements();
2634 unsigned WidenNumElts = NVT.getVectorNumElements();
2635 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2636 unsigned NumConcat = WidenNumElts / InNumElts;
2637 SmallVector<SDValue, 16> Ops(NumConcat);
2638 SDValue UndefVal = DAG.getUNDEF(InVT);
2639 Ops[0] = InOp;
2640 for (unsigned i = 1; i != NumConcat; ++i)
2641 Ops[i] = UndefVal;
2642
2643 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2644 }
2645
2646 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2647 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2648 DAG.getIntPtrConstant(0));
2649
2650 // Fall back to extract and build.
2651 SmallVector<SDValue, 16> Ops(WidenNumElts);
2652 EVT EltVT = NVT.getVectorElementType();
2653 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2654 unsigned Idx;
2655 for (Idx = 0; Idx < MinNumElts; ++Idx)
2656 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2657 DAG.getIntPtrConstant(Idx));
2658
2659 SDValue UndefVal = DAG.getUNDEF(EltVT);
2660 for ( ; Idx < WidenNumElts; ++Idx)
2661 Ops[Idx] = UndefVal;
2662 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);
2663 }
2664