1 //===-- MSP430InstrInfo.cpp - MSP430 Instruction Information --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MSP430InstrInfo.h"
15 #include "MSP430.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430TargetMachine.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
24
25 #define GET_INSTRINFO_CTOR
26 #include "MSP430GenInstrInfo.inc"
27
28 using namespace llvm;
29
MSP430InstrInfo(MSP430TargetMachine & tm)30 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
31 : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
32 RI(tm, *this), TM(tm) {}
33
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned SrcReg,bool isKill,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const34 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
35 MachineBasicBlock::iterator MI,
36 unsigned SrcReg, bool isKill, int FrameIdx,
37 const TargetRegisterClass *RC,
38 const TargetRegisterInfo *TRI) const {
39 DebugLoc DL;
40 if (MI != MBB.end()) DL = MI->getDebugLoc();
41 MachineFunction &MF = *MBB.getParent();
42 MachineFrameInfo &MFI = *MF.getFrameInfo();
43
44 MachineMemOperand *MMO =
45 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
46 MachineMemOperand::MOStore,
47 MFI.getObjectSize(FrameIdx),
48 MFI.getObjectAlignment(FrameIdx));
49
50 if (RC == &MSP430::GR16RegClass)
51 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
52 .addFrameIndex(FrameIdx).addImm(0)
53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
54 else if (RC == &MSP430::GR8RegClass)
55 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
56 .addFrameIndex(FrameIdx).addImm(0)
57 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
58 else
59 llvm_unreachable("Cannot store this register to stack slot!");
60 }
61
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned DestReg,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const62 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator MI,
64 unsigned DestReg, int FrameIdx,
65 const TargetRegisterClass *RC,
66 const TargetRegisterInfo *TRI) const{
67 DebugLoc DL;
68 if (MI != MBB.end()) DL = MI->getDebugLoc();
69 MachineFunction &MF = *MBB.getParent();
70 MachineFrameInfo &MFI = *MF.getFrameInfo();
71
72 MachineMemOperand *MMO =
73 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
74 MachineMemOperand::MOLoad,
75 MFI.getObjectSize(FrameIdx),
76 MFI.getObjectAlignment(FrameIdx));
77
78 if (RC == &MSP430::GR16RegClass)
79 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
80 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
81 else if (RC == &MSP430::GR8RegClass)
82 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
84 else
85 llvm_unreachable("Cannot store this register to stack slot!");
86 }
87
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,DebugLoc DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const88 void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
89 MachineBasicBlock::iterator I, DebugLoc DL,
90 unsigned DestReg, unsigned SrcReg,
91 bool KillSrc) const {
92 unsigned Opc;
93 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
94 Opc = MSP430::MOV16rr;
95 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
96 Opc = MSP430::MOV8rr;
97 else
98 llvm_unreachable("Impossible reg-to-reg copy");
99
100 BuildMI(MBB, I, DL, get(Opc), DestReg)
101 .addReg(SrcReg, getKillRegState(KillSrc));
102 }
103
RemoveBranch(MachineBasicBlock & MBB) const104 unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
105 MachineBasicBlock::iterator I = MBB.end();
106 unsigned Count = 0;
107
108 while (I != MBB.begin()) {
109 --I;
110 if (I->isDebugValue())
111 continue;
112 if (I->getOpcode() != MSP430::JMP &&
113 I->getOpcode() != MSP430::JCC &&
114 I->getOpcode() != MSP430::Br &&
115 I->getOpcode() != MSP430::Bm)
116 break;
117 // Remove the branch.
118 I->eraseFromParent();
119 I = MBB.end();
120 ++Count;
121 }
122
123 return Count;
124 }
125
126 bool MSP430InstrInfo::
ReverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const127 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
128 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
129
130 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
131
132 switch (CC) {
133 default: llvm_unreachable("Invalid branch condition!");
134 case MSP430CC::COND_E:
135 CC = MSP430CC::COND_NE;
136 break;
137 case MSP430CC::COND_NE:
138 CC = MSP430CC::COND_E;
139 break;
140 case MSP430CC::COND_L:
141 CC = MSP430CC::COND_GE;
142 break;
143 case MSP430CC::COND_GE:
144 CC = MSP430CC::COND_L;
145 break;
146 case MSP430CC::COND_HS:
147 CC = MSP430CC::COND_LO;
148 break;
149 case MSP430CC::COND_LO:
150 CC = MSP430CC::COND_HS;
151 break;
152 }
153
154 Cond[0].setImm(CC);
155 return false;
156 }
157
isUnpredicatedTerminator(const MachineInstr * MI) const158 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
159 if (!MI->isTerminator()) return false;
160
161 // Conditional branch is a special case.
162 if (MI->isBranch() && !MI->isBarrier())
163 return true;
164 if (!MI->isPredicable())
165 return true;
166 return !isPredicated(MI);
167 }
168
AnalyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const169 bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
170 MachineBasicBlock *&TBB,
171 MachineBasicBlock *&FBB,
172 SmallVectorImpl<MachineOperand> &Cond,
173 bool AllowModify) const {
174 // Start from the bottom of the block and work up, examining the
175 // terminator instructions.
176 MachineBasicBlock::iterator I = MBB.end();
177 while (I != MBB.begin()) {
178 --I;
179 if (I->isDebugValue())
180 continue;
181
182 // Working from the bottom, when we see a non-terminator
183 // instruction, we're done.
184 if (!isUnpredicatedTerminator(I))
185 break;
186
187 // A terminator that isn't a branch can't easily be handled
188 // by this analysis.
189 if (!I->isBranch())
190 return true;
191
192 // Cannot handle indirect branches.
193 if (I->getOpcode() == MSP430::Br ||
194 I->getOpcode() == MSP430::Bm)
195 return true;
196
197 // Handle unconditional branches.
198 if (I->getOpcode() == MSP430::JMP) {
199 if (!AllowModify) {
200 TBB = I->getOperand(0).getMBB();
201 continue;
202 }
203
204 // If the block has any instructions after a JMP, delete them.
205 while (llvm::next(I) != MBB.end())
206 llvm::next(I)->eraseFromParent();
207 Cond.clear();
208 FBB = 0;
209
210 // Delete the JMP if it's equivalent to a fall-through.
211 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
212 TBB = 0;
213 I->eraseFromParent();
214 I = MBB.end();
215 continue;
216 }
217
218 // TBB is used to indicate the unconditinal destination.
219 TBB = I->getOperand(0).getMBB();
220 continue;
221 }
222
223 // Handle conditional branches.
224 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
225 MSP430CC::CondCodes BranchCode =
226 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
227 if (BranchCode == MSP430CC::COND_INVALID)
228 return true; // Can't handle weird stuff.
229
230 // Working from the bottom, handle the first conditional branch.
231 if (Cond.empty()) {
232 FBB = TBB;
233 TBB = I->getOperand(0).getMBB();
234 Cond.push_back(MachineOperand::CreateImm(BranchCode));
235 continue;
236 }
237
238 // Handle subsequent conditional branches. Only handle the case where all
239 // conditional branches branch to the same destination.
240 assert(Cond.size() == 1);
241 assert(TBB);
242
243 // Only handle the case where all conditional branches branch to
244 // the same destination.
245 if (TBB != I->getOperand(0).getMBB())
246 return true;
247
248 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
249 // If the conditions are the same, we can leave them alone.
250 if (OldBranchCode == BranchCode)
251 continue;
252
253 return true;
254 }
255
256 return false;
257 }
258
259 unsigned
InsertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,const SmallVectorImpl<MachineOperand> & Cond,DebugLoc DL) const260 MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
261 MachineBasicBlock *FBB,
262 const SmallVectorImpl<MachineOperand> &Cond,
263 DebugLoc DL) const {
264 // Shouldn't be a fall through.
265 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
266 assert((Cond.size() == 1 || Cond.size() == 0) &&
267 "MSP430 branch conditions have one component!");
268
269 if (Cond.empty()) {
270 // Unconditional branch?
271 assert(!FBB && "Unconditional branch with multiple successors!");
272 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
273 return 1;
274 }
275
276 // Conditional branch.
277 unsigned Count = 0;
278 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
279 ++Count;
280
281 if (FBB) {
282 // Two-way Conditional branch. Insert the second branch.
283 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
284 ++Count;
285 }
286 return Count;
287 }
288
289 /// GetInstSize - Return the number of bytes of code the specified
290 /// instruction may be. This returns the maximum number of bytes.
291 ///
GetInstSizeInBytes(const MachineInstr * MI) const292 unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
293 const MCInstrDesc &Desc = MI->getDesc();
294
295 switch (Desc.TSFlags & MSP430II::SizeMask) {
296 default:
297 switch (Desc.getOpcode()) {
298 default: llvm_unreachable("Unknown instruction size!");
299 case TargetOpcode::PROLOG_LABEL:
300 case TargetOpcode::EH_LABEL:
301 case TargetOpcode::IMPLICIT_DEF:
302 case TargetOpcode::KILL:
303 case TargetOpcode::DBG_VALUE:
304 return 0;
305 case TargetOpcode::INLINEASM: {
306 const MachineFunction *MF = MI->getParent()->getParent();
307 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
308 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
309 *MF->getTarget().getMCAsmInfo());
310 }
311 }
312 case MSP430II::SizeSpecial:
313 switch (MI->getOpcode()) {
314 default: llvm_unreachable("Unknown instruction size!");
315 case MSP430::SAR8r1c:
316 case MSP430::SAR16r1c:
317 return 4;
318 }
319 case MSP430II::Size2Bytes:
320 return 2;
321 case MSP430II::Size4Bytes:
322 return 4;
323 case MSP430II::Size6Bytes:
324 return 6;
325 }
326 }
327