| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCallingConvLower.h | 111 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { in getFirstUnallocated()
138 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { in AllocateReg()
150 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, in AllocateReg()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterScavenging.h | 146 void setUsed(BitVector &Regs) { in setUsed()
149 void setUnused(BitVector &Regs) { in setUnused()
|
| D | CallingConvLower.h | 232 unsigned getFirstUnallocated(const uint16_t *Regs, unsigned NumRegs) const { in getFirstUnallocated()
259 unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) { in AllocateReg()
271 unsigned AllocateReg(const uint16_t *Regs, const uint16_t *ShadowRegs, in AllocateReg()
|
| D | MachineRegisterInfo.h | 351 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } in addPhysRegsUsed()
|
| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 134 const CodeGenRegister::Set &Regs = RC.getMembers(); in EmitRegUnitPressure() local
199 const std::vector<CodeGenRegister*> &Regs, in EmitRegMappingTables()
325 const std::vector<CodeGenRegister*> &Regs, in EmitRegMapping()
453 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); in runMCDesc() local
899 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); in runTargetDesc() local
1082 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc() local
|
| D | CodeGenRegisters.cpp | 100 RegUnitIterator(const CodeGenRegister::Set &Regs): in RegUnitIterator()
759 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local
934 CodeGenRegister::Set Regs; member
965 const CodeGenRegister::Set &Regs = RegClass->getMembers(); in computeUberSets() local
1605 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) { in computeCoveredRegisters()
|
| D | CodeGenTarget.cpp | 197 const std::vector<CodeGenRegister*> &Regs = getRegBank().getRegisters(); in getRegisterByName() local
|
| D | AsmMatcherEmitter.cpp | 1822 const std::vector<CodeGenRegister*> &Regs = in EmitMatchRegisterName() local
|
| /external/llvm/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 197 lookupCandidateBaseReg(const SmallVector<std::pair<unsigned, int64_t>, 8> &Regs, in lookupCandidateBaseReg()
|
| D | AggressiveAntiDepBreaker.cpp | 71 std::vector<unsigned> &Regs, in GetGroupRegs()
558 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
|
| D | ExecutionDepsFix.cpp | 575 SmallVector<LiveReg, 4> Regs; in visitSoftInstr() local
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 578 SmallVector<std::pair<unsigned,bool>, 4> Regs; in emitPushInst() local
648 SmallVector<unsigned, 4> Regs; in emitPopInst() local
|
| D | Thumb2SizeReduction.cpp | 192 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) in HasImplicitCPSRDef() local
|
| D | ARMLoadStoreOptimizer.cpp | 282 ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB, in MergeOps()
393 SmallVector<std::pair<unsigned, bool>, 8> Regs; in MergeOpsUpdate() local
|
| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 824 SmallPtrSet<const SCEV *, 16> &Regs, in RateRegister()
872 SmallPtrSet<const SCEV *, 16> &Regs, in RatePrimaryRegister()
888 SmallPtrSet<const SCEV *, 16> &Regs, in RateFormula()
1140 SmallPtrSet<const SCEV *, 4> Regs; member in __anon61c3719a0611::LSRUse
3592 SmallPtrSet<const SCEV *, 16> Regs; in FilterOutUndesirableDedicatedRegisters() local
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 577 SmallVector<unsigned, 4> Regs; member
5761 SmallVector<unsigned, 4> Regs; in GetRegistersForValue() local
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 2159 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, in CreateRegList()
|