• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implementation of the MachineRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Target/TargetMachine.h"
18 using namespace llvm;
19 
MachineRegisterInfo(const TargetRegisterInfo & TRI)20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
21   : TRI(&TRI), IsSSA(true), TracksLiveness(true) {
22   VRegInfo.reserve(256);
23   RegAllocHints.reserve(256);
24   UsedPhysRegs.resize(TRI.getNumRegs());
25   UsedPhysRegMask.resize(TRI.getNumRegs());
26 
27   // Create the physreg use/def lists.
28   PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
29   memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
30 }
31 
~MachineRegisterInfo()32 MachineRegisterInfo::~MachineRegisterInfo() {
33 #ifndef NDEBUG
34   clearVirtRegs();
35   for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
36     assert(!PhysRegUseDefLists[i] &&
37            "PhysRegUseDefLists has entries after all instructions are deleted");
38 #endif
39   delete [] PhysRegUseDefLists;
40 }
41 
42 /// setRegClass - Set the register class of the specified virtual register.
43 ///
44 void
setRegClass(unsigned Reg,const TargetRegisterClass * RC)45 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
46   VRegInfo[Reg].first = RC;
47 }
48 
49 const TargetRegisterClass *
constrainRegClass(unsigned Reg,const TargetRegisterClass * RC,unsigned MinNumRegs)50 MachineRegisterInfo::constrainRegClass(unsigned Reg,
51                                        const TargetRegisterClass *RC,
52                                        unsigned MinNumRegs) {
53   const TargetRegisterClass *OldRC = getRegClass(Reg);
54   if (OldRC == RC)
55     return RC;
56   const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
57   if (!NewRC || NewRC == OldRC)
58     return NewRC;
59   if (NewRC->getNumRegs() < MinNumRegs)
60     return 0;
61   setRegClass(Reg, NewRC);
62   return NewRC;
63 }
64 
65 bool
recomputeRegClass(unsigned Reg,const TargetMachine & TM)66 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
67   const TargetInstrInfo *TII = TM.getInstrInfo();
68   const TargetRegisterClass *OldRC = getRegClass(Reg);
69   const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
70 
71   // Stop early if there is no room to grow.
72   if (NewRC == OldRC)
73     return false;
74 
75   // Accumulate constraints from all uses.
76   for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
77        ++I) {
78     const TargetRegisterClass *OpRC =
79       I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
80     if (unsigned SubIdx = I.getOperand().getSubReg()) {
81       if (OpRC)
82         NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx);
83       else
84         NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx);
85     } else if (OpRC)
86       NewRC = TRI->getCommonSubClass(NewRC, OpRC);
87     if (!NewRC || NewRC == OldRC)
88       return false;
89   }
90   setRegClass(Reg, NewRC);
91   return true;
92 }
93 
94 /// createVirtualRegister - Create and return a new virtual register in the
95 /// function with the specified register class.
96 ///
97 unsigned
createVirtualRegister(const TargetRegisterClass * RegClass)98 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
99   assert(RegClass && "Cannot create register without RegClass!");
100   assert(RegClass->isAllocatable() &&
101          "Virtual register RegClass must be allocatable.");
102 
103   // New virtual register number.
104   unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
105 
106   // Add a reg, but keep track of whether the vector reallocated or not.
107   const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0);
108   void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg];
109   VRegInfo.grow(Reg);
110   VRegInfo[Reg].first = RegClass;
111   RegAllocHints.grow(Reg);
112 
113   if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase)
114     // The vector reallocated, handle this now.
115     HandleVRegListReallocation();
116   return Reg;
117 }
118 
119 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
clearVirtRegs()120 void MachineRegisterInfo::clearVirtRegs() {
121 #ifndef NDEBUG
122   for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
123     assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 &&
124            "Vreg use list non-empty still?");
125 #endif
126   VRegInfo.clear();
127 }
128 
129 /// HandleVRegListReallocation - We just added a virtual register to the
130 /// VRegInfo info list and it reallocated.  Update the use/def lists info
131 /// pointers.
HandleVRegListReallocation()132 void MachineRegisterInfo::HandleVRegListReallocation() {
133   // The back pointers for the vreg lists point into the previous vector.
134   // Update them to point to their correct slots.
135   for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
136     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
137     MachineOperand *List = VRegInfo[Reg].second;
138     if (!List) continue;
139     // Update the back-pointer to be accurate once more.
140     List->Contents.Reg.Prev = &VRegInfo[Reg].second;
141   }
142 }
143 
144 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
145 /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
146 /// except that it also changes any definitions of the register as well.
replaceRegWith(unsigned FromReg,unsigned ToReg)147 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
148   assert(FromReg != ToReg && "Cannot replace a reg with itself");
149 
150   // TODO: This could be more efficient by bulk changing the operands.
151   for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
152     MachineOperand &O = I.getOperand();
153     ++I;
154     O.setReg(ToReg);
155   }
156 }
157 
158 
159 /// getVRegDef - Return the machine instr that defines the specified virtual
160 /// register or null if none is found.  This assumes that the code is in SSA
161 /// form, so there should only be one definition.
getVRegDef(unsigned Reg) const162 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
163   // Since we are in SSA form, we can use the first definition.
164   def_iterator I = def_begin(Reg);
165   return !I.atEnd() ? &*I : 0;
166 }
167 
hasOneUse(unsigned RegNo) const168 bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const {
169   use_iterator UI = use_begin(RegNo);
170   if (UI == use_end())
171     return false;
172   return ++UI == use_end();
173 }
174 
hasOneNonDBGUse(unsigned RegNo) const175 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
176   use_nodbg_iterator UI = use_nodbg_begin(RegNo);
177   if (UI == use_nodbg_end())
178     return false;
179   return ++UI == use_nodbg_end();
180 }
181 
182 /// clearKillFlags - Iterate over all the uses of the given register and
183 /// clear the kill flag from the MachineOperand. This function is used by
184 /// optimization passes which extend register lifetimes and need only
185 /// preserve conservative kill flag information.
clearKillFlags(unsigned Reg) const186 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
187   for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
188     UI.getOperand().setIsKill(false);
189 }
190 
isLiveIn(unsigned Reg) const191 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
192   for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
193     if (I->first == Reg || I->second == Reg)
194       return true;
195   return false;
196 }
197 
isLiveOut(unsigned Reg) const198 bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
199   for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
200     if (*I == Reg)
201       return true;
202   return false;
203 }
204 
205 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
206 /// corresponding live-in physical register.
getLiveInPhysReg(unsigned VReg) const207 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
208   for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
209     if (I->second == VReg)
210       return I->first;
211   return 0;
212 }
213 
214 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
215 /// corresponding live-in physical register.
getLiveInVirtReg(unsigned PReg) const216 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
217   for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
218     if (I->first == PReg)
219       return I->second;
220   return 0;
221 }
222 
223 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
224 /// into the given entry block.
225 void
EmitLiveInCopies(MachineBasicBlock * EntryMBB,const TargetRegisterInfo & TRI,const TargetInstrInfo & TII)226 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
227                                       const TargetRegisterInfo &TRI,
228                                       const TargetInstrInfo &TII) {
229   // Emit the copies into the top of the block.
230   for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
231     if (LiveIns[i].second) {
232       if (use_empty(LiveIns[i].second)) {
233         // The livein has no uses. Drop it.
234         //
235         // It would be preferable to have isel avoid creating live-in
236         // records for unused arguments in the first place, but it's
237         // complicated by the debug info code for arguments.
238         LiveIns.erase(LiveIns.begin() + i);
239         --i; --e;
240       } else {
241         // Emit a copy.
242         BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
243                 TII.get(TargetOpcode::COPY), LiveIns[i].second)
244           .addReg(LiveIns[i].first);
245 
246         // Add the register to the entry block live-in set.
247         EntryMBB->addLiveIn(LiveIns[i].first);
248       }
249     } else {
250       // Add the register to the entry block live-in set.
251       EntryMBB->addLiveIn(LiveIns[i].first);
252     }
253 }
254 
255 #ifndef NDEBUG
dumpUses(unsigned Reg) const256 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
257   for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
258     I.getOperand().getParent()->dump();
259 }
260 #endif
261 
freezeReservedRegs(const MachineFunction & MF)262 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
263   ReservedRegs = TRI->getReservedRegs(MF);
264 }
265 
isConstantPhysReg(unsigned PhysReg,const MachineFunction & MF) const266 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
267                                             const MachineFunction &MF) const {
268   assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
269 
270   // Check if any overlapping register is modified.
271   for (const uint16_t *R = TRI->getOverlaps(PhysReg); *R; ++R)
272     if (!def_empty(*R))
273       return false;
274 
275   // Check if any overlapping register is allocatable so it may be used later.
276   if (AllocatableRegs.empty())
277     AllocatableRegs = TRI->getAllocatableSet(MF);
278   for (const uint16_t *R = TRI->getOverlaps(PhysReg); *R; ++R)
279     if (AllocatableRegs.test(*R))
280       return false;
281   return true;
282 }
283