1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28
29 enum {
30 TLBRET_DIRTY = -4,
31 TLBRET_INVALID = -3,
32 TLBRET_NOMATCH = -2,
33 TLBRET_BADADDR = -1,
34 TLBRET_MATCH = 0
35 };
36
37 /* no MMU emulation */
no_mmu_map_address(CPUState * env,target_phys_addr_t * physical,int * prot,target_ulong address,int rw,int access_type)38 int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
39 target_ulong address, int rw, int access_type)
40 {
41 *physical = address;
42 *prot = PAGE_READ | PAGE_WRITE;
43 return TLBRET_MATCH;
44 }
45
46 /* fixed mapping MMU emulation */
fixed_mmu_map_address(CPUState * env,target_phys_addr_t * physical,int * prot,target_ulong address,int rw,int access_type)47 int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
48 target_ulong address, int rw, int access_type)
49 {
50 if (address <= (int32_t)0x7FFFFFFFUL) {
51 if (!(env->CP0_Status & (1 << CP0St_ERL)))
52 *physical = address + 0x40000000UL;
53 else
54 *physical = address;
55 } else if (address <= (int32_t)0xBFFFFFFFUL)
56 *physical = address & 0x1FFFFFFF;
57 else
58 *physical = address;
59
60 *prot = PAGE_READ | PAGE_WRITE;
61 return TLBRET_MATCH;
62 }
63
64 /* MIPS32/MIPS64 R4000-style MMU emulation */
r4k_map_address(CPUState * env,target_phys_addr_t * physical,int * prot,target_ulong address,int rw,int access_type)65 int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
66 target_ulong address, int rw, int access_type)
67 {
68 uint8_t ASID = env->CP0_EntryHi & 0xFF;
69 int i;
70
71 for (i = 0; i < env->tlb->tlb_in_use; i++) {
72 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
73 /* 1k pages are not supported. */
74 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
75 target_ulong tag = address & ~mask;
76 target_ulong VPN = tlb->VPN & ~mask;
77 #if defined(TARGET_MIPS64)
78 tag &= env->SEGMask;
79 #endif
80
81 /* Check ASID, virtual page number & size */
82 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
83 /* TLB match */
84 int n = !!(address & mask & ~(mask >> 1));
85 /* Check access rights */
86 if (!(n ? tlb->V1 : tlb->V0))
87 return TLBRET_INVALID;
88 if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
89 *physical = tlb->PFN[n] | (address & (mask >> 1));
90 *prot = PAGE_READ;
91 if (n ? tlb->D1 : tlb->D0)
92 *prot |= PAGE_WRITE;
93 return TLBRET_MATCH;
94 }
95 return TLBRET_DIRTY;
96 }
97 }
98 return TLBRET_NOMATCH;
99 }
100
101 #if !defined(CONFIG_USER_ONLY)
get_physical_address(CPUState * env,target_phys_addr_t * physical,int * prot,target_ulong address,int rw,int access_type)102 static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
103 int *prot, target_ulong address,
104 int rw, int access_type)
105 {
106 /* User mode can only access useg/xuseg */
107 int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
108 int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
109 int kernel_mode = !user_mode && !supervisor_mode;
110 #if defined(TARGET_MIPS64)
111 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
112 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
113 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
114 #endif
115 int ret = TLBRET_MATCH;
116
117 #if 0
118 qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
119 #endif
120
121 if (address <= (int32_t)0x7FFFFFFFUL) {
122 /* useg */
123 if (env->CP0_Status & (1 << CP0St_ERL)) {
124 *physical = address & 0xFFFFFFFF;
125 *prot = PAGE_READ | PAGE_WRITE;
126 } else {
127 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
128 }
129 #if defined(TARGET_MIPS64)
130 } else if (address < 0x4000000000000000ULL) {
131 /* xuseg */
132 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
133 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
134 } else {
135 ret = TLBRET_BADADDR;
136 }
137 } else if (address < 0x8000000000000000ULL) {
138 /* xsseg */
139 if ((supervisor_mode || kernel_mode) &&
140 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
141 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
142 } else {
143 ret = TLBRET_BADADDR;
144 }
145 } else if (address < 0xC000000000000000ULL) {
146 /* xkphys */
147 if (kernel_mode && KX &&
148 (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
149 *physical = address & env->PAMask;
150 *prot = PAGE_READ | PAGE_WRITE;
151 } else {
152 ret = TLBRET_BADADDR;
153 }
154 } else if (address < 0xFFFFFFFF80000000ULL) {
155 /* xkseg */
156 if (kernel_mode && KX &&
157 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
158 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
159 } else {
160 ret = TLBRET_BADADDR;
161 }
162 #endif
163 } else if (address < (int32_t)0xA0000000UL) {
164 /* kseg0 */
165 if (kernel_mode) {
166 *physical = address - (int32_t)0x80000000UL;
167 *prot = PAGE_READ | PAGE_WRITE;
168 } else {
169 ret = TLBRET_BADADDR;
170 }
171 } else if (address < (int32_t)0xC0000000UL) {
172 /* kseg1 */
173 if (kernel_mode) {
174 *physical = address - (int32_t)0xA0000000UL;
175 *prot = PAGE_READ | PAGE_WRITE;
176 } else {
177 ret = TLBRET_BADADDR;
178 }
179 } else if (address < (int32_t)0xE0000000UL) {
180 /* sseg (kseg2) */
181 if (supervisor_mode || kernel_mode) {
182 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
183 } else {
184 ret = TLBRET_BADADDR;
185 }
186 } else {
187 /* kseg3 */
188 /* XXX: debug segment is not emulated */
189 if (kernel_mode) {
190 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
191 } else {
192 ret = TLBRET_BADADDR;
193 }
194 }
195 #if 0
196 qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
197 address, rw, access_type, *physical, *prot, ret);
198 #endif
199
200 return ret;
201 }
202 #endif
203
raise_mmu_exception(CPUState * env,target_ulong address,int rw,int tlb_error)204 static void raise_mmu_exception(CPUState *env, target_ulong address,
205 int rw, int tlb_error)
206 {
207 int exception = 0, error_code = 0;
208
209 switch (tlb_error) {
210 default:
211 case TLBRET_BADADDR:
212 /* Reference to kernel address from user mode or supervisor mode */
213 /* Reference to supervisor address from user mode */
214 if (rw)
215 exception = EXCP_AdES;
216 else
217 exception = EXCP_AdEL;
218 break;
219 case TLBRET_NOMATCH:
220 /* No TLB match for a mapped address */
221 if (rw)
222 exception = EXCP_TLBS;
223 else
224 exception = EXCP_TLBL;
225 error_code = 1;
226 break;
227 case TLBRET_INVALID:
228 /* TLB match with no valid bit */
229 if (rw)
230 exception = EXCP_TLBS;
231 else
232 exception = EXCP_TLBL;
233 break;
234 case TLBRET_DIRTY:
235 /* TLB match but 'D' bit is cleared */
236 exception = EXCP_LTLBL;
237 break;
238
239 }
240 /* Raise exception */
241 env->CP0_BadVAddr = address;
242 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
243 ((address >> 9) & 0x007ffff0);
244 env->CP0_EntryHi =
245 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
246 #if defined(TARGET_MIPS64)
247 env->CP0_EntryHi &= env->SEGMask;
248 env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
249 ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
250 ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
251 #endif
252 env->exception_index = exception;
253 env->error_code = error_code;
254 }
255
cpu_get_phys_page_debug(CPUState * env,target_ulong addr)256 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
257 {
258 #if defined(CONFIG_USER_ONLY)
259 return addr;
260 #else
261 target_phys_addr_t phys_addr;
262 int prot;
263
264 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
265 return -1;
266 return phys_addr;
267 #endif
268 }
269
cpu_mips_handle_mmu_fault(CPUState * env,target_ulong address,int rw,int mmu_idx,int is_softmmu)270 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
271 int mmu_idx, int is_softmmu)
272 {
273 #if !defined(CONFIG_USER_ONLY)
274 target_phys_addr_t physical;
275 int prot;
276 #endif
277 int access_type;
278 int ret = 0;
279
280 #if 0
281 log_cpu_state(env, 0);
282 #endif
283 qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",
284 __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu);
285
286 rw &= 1;
287
288 /* data access */
289 /* XXX: put correct access by using cpu_restore_state()
290 correctly */
291 access_type = ACCESS_INT;
292 #if defined(CONFIG_USER_ONLY)
293 ret = TLBRET_NOMATCH;
294 #else
295 ret = get_physical_address(env, &physical, &prot,
296 address, rw, access_type);
297 qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n",
298 __func__, address, ret, physical, prot);
299 if (ret == TLBRET_MATCH) {
300 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
301 physical & TARGET_PAGE_MASK, prot,
302 mmu_idx, is_softmmu);
303 } else if (ret < 0)
304 #endif
305 {
306 raise_mmu_exception(env, address, rw, ret);
307 ret = 1;
308 }
309
310 return ret;
311 }
312
313 #if !defined(CONFIG_USER_ONLY)
cpu_mips_translate_address(CPUState * env,target_ulong address,int rw)314 target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw)
315 {
316 target_phys_addr_t physical;
317 int prot;
318 int access_type;
319 int ret = 0;
320
321 rw &= 1;
322
323 /* data access */
324 access_type = ACCESS_INT;
325 ret = get_physical_address(env, &physical, &prot,
326 address, rw, access_type);
327 if (ret != TLBRET_MATCH) {
328 raise_mmu_exception(env, address, rw, ret);
329 return -1LL;
330 } else {
331 return physical;
332 }
333 }
334 #endif
335
336 static const char * const excp_names[EXCP_LAST + 1] = {
337 [EXCP_RESET] = "reset",
338 [EXCP_SRESET] = "soft reset",
339 [EXCP_DSS] = "debug single step",
340 [EXCP_DINT] = "debug interrupt",
341 [EXCP_NMI] = "non-maskable interrupt",
342 [EXCP_MCHECK] = "machine check",
343 [EXCP_EXT_INTERRUPT] = "interrupt",
344 [EXCP_DFWATCH] = "deferred watchpoint",
345 [EXCP_DIB] = "debug instruction breakpoint",
346 [EXCP_IWATCH] = "instruction fetch watchpoint",
347 [EXCP_AdEL] = "address error load",
348 [EXCP_AdES] = "address error store",
349 [EXCP_TLBF] = "TLB refill",
350 [EXCP_IBE] = "instruction bus error",
351 [EXCP_DBp] = "debug breakpoint",
352 [EXCP_SYSCALL] = "syscall",
353 [EXCP_BREAK] = "break",
354 [EXCP_CpU] = "coprocessor unusable",
355 [EXCP_RI] = "reserved instruction",
356 [EXCP_OVERFLOW] = "arithmetic overflow",
357 [EXCP_TRAP] = "trap",
358 [EXCP_FPE] = "floating point",
359 [EXCP_DDBS] = "debug data break store",
360 [EXCP_DWATCH] = "data watchpoint",
361 [EXCP_LTLBL] = "TLB modify",
362 [EXCP_TLBL] = "TLB load",
363 [EXCP_TLBS] = "TLB store",
364 [EXCP_DBE] = "data bus error",
365 [EXCP_DDBL] = "debug data break load",
366 [EXCP_THREAD] = "thread",
367 [EXCP_MDMX] = "MDMX",
368 [EXCP_C2E] = "precise coprocessor 2",
369 [EXCP_CACHE] = "cache error",
370 };
371
do_interrupt(CPUState * env)372 void do_interrupt (CPUState *env)
373 {
374 #if !defined(CONFIG_USER_ONLY)
375 target_ulong offset;
376 int cause = -1;
377 const char *name;
378
379 if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
380 if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
381 name = "unknown";
382 else
383 name = excp_names[env->exception_index];
384
385 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
386 __func__, env->active_tc.PC, env->CP0_EPC, name);
387 }
388 if (env->exception_index == EXCP_EXT_INTERRUPT &&
389 (env->hflags & MIPS_HFLAG_DM))
390 env->exception_index = EXCP_DINT;
391 offset = 0x180;
392 switch (env->exception_index) {
393 case EXCP_DSS:
394 env->CP0_Debug |= 1 << CP0DB_DSS;
395 /* Debug single step cannot be raised inside a delay slot and
396 resume will always occur on the next instruction
397 (but we assume the pc has always been updated during
398 code translation). */
399 env->CP0_DEPC = env->active_tc.PC;
400 goto enter_debug_mode;
401 case EXCP_DINT:
402 env->CP0_Debug |= 1 << CP0DB_DINT;
403 goto set_DEPC;
404 case EXCP_DIB:
405 env->CP0_Debug |= 1 << CP0DB_DIB;
406 goto set_DEPC;
407 case EXCP_DBp:
408 env->CP0_Debug |= 1 << CP0DB_DBp;
409 goto set_DEPC;
410 case EXCP_DDBS:
411 env->CP0_Debug |= 1 << CP0DB_DDBS;
412 goto set_DEPC;
413 case EXCP_DDBL:
414 env->CP0_Debug |= 1 << CP0DB_DDBL;
415 set_DEPC:
416 if (env->hflags & MIPS_HFLAG_BMASK) {
417 /* If the exception was raised from a delay slot,
418 come back to the jump. */
419 env->CP0_DEPC = env->active_tc.PC - 4;
420 env->hflags &= ~MIPS_HFLAG_BMASK;
421 } else {
422 env->CP0_DEPC = env->active_tc.PC;
423 }
424 enter_debug_mode:
425 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
426 env->hflags &= ~(MIPS_HFLAG_KSU);
427 /* EJTAG probe trap enable is not implemented... */
428 if (!(env->CP0_Status & (1 << CP0St_EXL)))
429 env->CP0_Cause &= ~(1 << CP0Ca_BD);
430 env->active_tc.PC = (int32_t)0xBFC00480;
431 break;
432 case EXCP_RESET:
433 cpu_reset(env);
434 break;
435 case EXCP_SRESET:
436 env->CP0_Status |= (1 << CP0St_SR);
437 memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
438 goto set_error_EPC;
439 case EXCP_NMI:
440 env->CP0_Status |= (1 << CP0St_NMI);
441 set_error_EPC:
442 if (env->hflags & MIPS_HFLAG_BMASK) {
443 /* If the exception was raised from a delay slot,
444 come back to the jump. */
445 env->CP0_ErrorEPC = env->active_tc.PC - 4;
446 env->hflags &= ~MIPS_HFLAG_BMASK;
447 } else {
448 env->CP0_ErrorEPC = env->active_tc.PC;
449 }
450 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
451 env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
452 env->hflags &= ~(MIPS_HFLAG_KSU);
453 if (!(env->CP0_Status & (1 << CP0St_EXL)))
454 env->CP0_Cause &= ~(1 << CP0Ca_BD);
455 env->active_tc.PC = (int32_t)0xBFC00000;
456 break;
457 case EXCP_EXT_INTERRUPT:
458 cause = 0;
459 if (env->CP0_Cause & (1 << CP0Ca_IV))
460 offset = 0x200;
461 goto set_EPC;
462 case EXCP_LTLBL:
463 cause = 1;
464 goto set_EPC;
465 case EXCP_TLBL:
466 cause = 2;
467 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
468 #if defined(TARGET_MIPS64)
469 int R = env->CP0_BadVAddr >> 62;
470 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
471 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
472 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
473
474 if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
475 offset = 0x080;
476 else
477 #endif
478 offset = 0x000;
479 }
480 goto set_EPC;
481 case EXCP_TLBS:
482 cause = 3;
483 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
484 #if defined(TARGET_MIPS64)
485 int R = env->CP0_BadVAddr >> 62;
486 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
487 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
488 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
489
490 if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
491 offset = 0x080;
492 else
493 #endif
494 offset = 0x000;
495 }
496 goto set_EPC;
497 case EXCP_AdEL:
498 cause = 4;
499 goto set_EPC;
500 case EXCP_AdES:
501 cause = 5;
502 goto set_EPC;
503 case EXCP_IBE:
504 cause = 6;
505 goto set_EPC;
506 case EXCP_DBE:
507 cause = 7;
508 goto set_EPC;
509 case EXCP_SYSCALL:
510 cause = 8;
511 goto set_EPC;
512 case EXCP_BREAK:
513 cause = 9;
514 goto set_EPC;
515 case EXCP_RI:
516 cause = 10;
517 goto set_EPC;
518 case EXCP_CpU:
519 cause = 11;
520 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
521 (env->error_code << CP0Ca_CE);
522 goto set_EPC;
523 case EXCP_OVERFLOW:
524 cause = 12;
525 goto set_EPC;
526 case EXCP_TRAP:
527 cause = 13;
528 goto set_EPC;
529 case EXCP_FPE:
530 cause = 15;
531 goto set_EPC;
532 case EXCP_C2E:
533 cause = 18;
534 goto set_EPC;
535 case EXCP_MDMX:
536 cause = 22;
537 goto set_EPC;
538 case EXCP_DWATCH:
539 cause = 23;
540 /* XXX: TODO: manage defered watch exceptions */
541 goto set_EPC;
542 case EXCP_MCHECK:
543 cause = 24;
544 goto set_EPC;
545 case EXCP_THREAD:
546 cause = 25;
547 goto set_EPC;
548 case EXCP_CACHE:
549 cause = 30;
550 if (env->CP0_Status & (1 << CP0St_BEV)) {
551 offset = 0x100;
552 } else {
553 offset = 0x20000100;
554 }
555 set_EPC:
556 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
557 if (env->hflags & MIPS_HFLAG_BMASK) {
558 /* If the exception was raised from a delay slot,
559 come back to the jump. */
560 env->CP0_EPC = env->active_tc.PC - 4;
561 env->CP0_Cause |= (1 << CP0Ca_BD);
562 } else {
563 env->CP0_EPC = env->active_tc.PC;
564 env->CP0_Cause &= ~(1 << CP0Ca_BD);
565 }
566 env->CP0_Status |= (1 << CP0St_EXL);
567 env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
568 env->hflags &= ~(MIPS_HFLAG_KSU);
569 }
570 env->hflags &= ~MIPS_HFLAG_BMASK;
571 if (env->CP0_Status & (1 << CP0St_BEV)) {
572 env->active_tc.PC = (int32_t)0xBFC00200;
573 } else {
574 env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
575 }
576 env->active_tc.PC += offset;
577 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
578 break;
579 default:
580 qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
581 printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
582 exit(1);
583 }
584 if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
585 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
586 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
587 __func__, env->active_tc.PC, env->CP0_EPC, cause,
588 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
589 env->CP0_DEPC);
590 }
591 #endif
592 env->exception_index = EXCP_NONE;
593 }
594
r4k_invalidate_tlb(CPUState * env,int idx,int use_extra)595 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
596 {
597 r4k_tlb_t *tlb;
598 target_ulong addr;
599 target_ulong end;
600 uint8_t ASID = env->CP0_EntryHi & 0xFF;
601 target_ulong mask;
602
603 tlb = &env->tlb->mmu.r4k.tlb[idx];
604 /* The qemu TLB is flushed when the ASID changes, so no need to
605 flush these entries again. */
606 if (tlb->G == 0 && tlb->ASID != ASID) {
607 return;
608 }
609
610 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
611 /* For tlbwr, we can shadow the discarded entry into
612 a new (fake) TLB entry, as long as the guest can not
613 tell that it's there. */
614 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
615 env->tlb->tlb_in_use++;
616 return;
617 }
618
619 /* 1k pages are not supported. */
620 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
621 if (tlb->V0) {
622 addr = tlb->VPN & ~mask;
623 #if defined(TARGET_MIPS64)
624 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
625 addr |= 0x3FFFFF0000000000ULL;
626 }
627 #endif
628 end = addr | (mask >> 1);
629 while (addr < end) {
630 tlb_flush_page (env, addr);
631 addr += TARGET_PAGE_SIZE;
632 }
633 }
634 if (tlb->V1) {
635 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
636 #if defined(TARGET_MIPS64)
637 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
638 addr |= 0x3FFFFF0000000000ULL;
639 }
640 #endif
641 end = addr | mask;
642 while (addr - 1 < end) {
643 tlb_flush_page (env, addr);
644 addr += TARGET_PAGE_SIZE;
645 }
646 }
647 }
648