1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #define DEBUG_TYPE "jit"
16 #include "ARM.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMBaseInstrInfo.h"
19 #include "ARMRelocations.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #ifndef NDEBUG
39 #include <iomanip>
40 #endif
41 using namespace llvm;
42
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45 namespace {
46
47 class ARMCodeEmitter : public MachineFunctionPass {
48 ARMJITInfo *JTI;
49 const ARMBaseInstrInfo *II;
50 const TargetData *TD;
51 const ARMSubtarget *Subtarget;
52 TargetMachine &TM;
53 JITCodeEmitter &MCE;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
57 bool IsPIC;
58 bool IsThumb;
59
getAnalysisUsage(AnalysisUsage & AU) const60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
63 }
64
65 static char ID;
66 public:
ARMCodeEmitter(TargetMachine & tm,JITCodeEmitter & mce)67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMBaseInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
78
79 bool runOnMachineFunction(MachineFunction &MF);
80
getPassName() const81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
83 }
84
85 void emitInstruction(const MachineInstr &MI);
86
87 private:
88
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstantToMemory(unsigned CPI, const Constant *CV);
92 void emitConstPoolInstruction(const MachineInstr &MI);
93 void emitMOVi32immInstruction(const MachineInstr &MI);
94 void emitMOVi2piecesInstruction(const MachineInstr &MI);
95 void emitLEApcrelInstruction(const MachineInstr &MI);
96 void emitLEApcrelJTInstruction(const MachineInstr &MI);
97 void emitPseudoMoveInstruction(const MachineInstr &MI);
98 void addPCLabel(unsigned LabelID);
99 void emitPseudoInstruction(const MachineInstr &MI);
100 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
101 const MCInstrDesc &MCID,
102 const MachineOperand &MO,
103 unsigned OpIdx);
104
105 unsigned getMachineSoImmOpValue(unsigned SoImm);
106 unsigned getAddrModeSBit(const MachineInstr &MI,
107 const MCInstrDesc &MCID) const;
108
109 void emitDataProcessingInstruction(const MachineInstr &MI,
110 unsigned ImplicitRd = 0,
111 unsigned ImplicitRn = 0);
112
113 void emitLoadStoreInstruction(const MachineInstr &MI,
114 unsigned ImplicitRd = 0,
115 unsigned ImplicitRn = 0);
116
117 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
118 unsigned ImplicitRn = 0);
119
120 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
121
122 void emitMulFrmInstruction(const MachineInstr &MI);
123
124 void emitExtendInstruction(const MachineInstr &MI);
125
126 void emitMiscArithInstruction(const MachineInstr &MI);
127
128 void emitSaturateInstruction(const MachineInstr &MI);
129
130 void emitBranchInstruction(const MachineInstr &MI);
131
132 void emitInlineJumpTable(unsigned JTIndex);
133
134 void emitMiscBranchInstruction(const MachineInstr &MI);
135
136 void emitVFPArithInstruction(const MachineInstr &MI);
137
138 void emitVFPConversionInstruction(const MachineInstr &MI);
139
140 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
141
142 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
143
144 void emitMiscInstruction(const MachineInstr &MI);
145
146 void emitNEONLaneInstruction(const MachineInstr &MI);
147 void emitNEONDupInstruction(const MachineInstr &MI);
148 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
149 void emitNEON2RegInstruction(const MachineInstr &MI);
150 void emitNEON3RegInstruction(const MachineInstr &MI);
151
152 /// getMachineOpValue - Return binary encoding of operand. If the machine
153 /// operand requires relocation, record the relocation and return zero.
154 unsigned getMachineOpValue(const MachineInstr &MI,
155 const MachineOperand &MO) const;
getMachineOpValue(const MachineInstr & MI,unsigned OpIdx) const156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
157 return getMachineOpValue(MI, MI.getOperand(OpIdx));
158 }
159
160 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
161 // TableGen'erated getBinaryCodeForInstr() function to encode any
162 // operand values, instead querying getMachineOpValue() directly for
163 // each operand it needs to encode. Thus, any of the new encoder
164 // helper functions can simply return 0 as the values the return
165 // are already handled elsewhere. They are placeholders to allow this
166 // encoder to continue to function until the MC encoder is sufficiently
167 // far along that this one can be eliminated entirely.
NEONThumb2DataIPostEncoder(const MachineInstr & MI,unsigned Val) const168 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
169 const { return 0; }
NEONThumb2LoadStorePostEncoder(const MachineInstr & MI,unsigned Val) const170 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
171 const { return 0; }
NEONThumb2DupPostEncoder(const MachineInstr & MI,unsigned Val) const172 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
173 const { return 0; }
VFPThumb2PostEncoder(const MachineInstr & MI,unsigned Val) const174 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val)
175 const {
176 if (IsThumb) {
177 Val &= 0x0FFFFFFF;
178 Val |= 0xE0000000;
179 }
180 return Val;
181 }
getAdrLabelOpValue(const MachineInstr & MI,unsigned Op) const182 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
183 const { return 0; }
getThumbAdrLabelOpValue(const MachineInstr & MI,unsigned Op) const184 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
185 const { return 0; }
getThumbBLTargetOpValue(const MachineInstr & MI,unsigned Op) const186 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
187 const { return 0; }
getThumbBLXTargetOpValue(const MachineInstr & MI,unsigned Op) const188 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
189 const { return 0; }
getThumbBRTargetOpValue(const MachineInstr & MI,unsigned Op) const190 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
191 const { return 0; }
getThumbBCCTargetOpValue(const MachineInstr & MI,unsigned Op) const192 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op)
193 const { return 0; }
getThumbCBTargetOpValue(const MachineInstr & MI,unsigned Op) const194 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op)
195 const { return 0; }
getBranchTargetOpValue(const MachineInstr & MI,unsigned Op) const196 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
197 const { return 0; }
getUnconditionalBranchTargetOpValue(const MachineInstr & MI,unsigned Op) const198 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI,
199 unsigned Op) const { return 0; }
getARMBranchTargetOpValue(const MachineInstr & MI,unsigned Op) const200 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
201 const { return 0; }
getARMBLTargetOpValue(const MachineInstr & MI,unsigned Op) const202 unsigned getARMBLTargetOpValue(const MachineInstr &MI, unsigned Op)
203 const { return 0; }
getARMBLXTargetOpValue(const MachineInstr & MI,unsigned Op) const204 unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
205 const { return 0; }
getCCOutOpValue(const MachineInstr & MI,unsigned Op) const206 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
207 const { return 0; }
getSOImmOpValue(const MachineInstr & MI,unsigned Op) const208 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
209 const { return 0; }
getT2SOImmOpValue(const MachineInstr & MI,unsigned Op) const210 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
211 const { return 0; }
getSORegRegOpValue(const MachineInstr & MI,unsigned Op) const212 unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op)
213 const { return 0; }
getSORegImmOpValue(const MachineInstr & MI,unsigned Op) const214 unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op)
215 const { return 0; }
getThumbAddrModeRegRegOpValue(const MachineInstr & MI,unsigned Op) const216 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
217 const { return 0; }
getT2AddrModeImm12OpValue(const MachineInstr & MI,unsigned Op) const218 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
219 const { return 0; }
getT2AddrModeImm8OpValue(const MachineInstr & MI,unsigned Op) const220 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
221 const { return 0; }
getT2Imm8s4OpValue(const MachineInstr & MI,unsigned Op) const222 unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op)
223 const { return 0; }
getT2AddrModeImm8s4OpValue(const MachineInstr & MI,unsigned Op) const224 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
225 const { return 0; }
getT2AddrModeImm0_1020s4OpValue(const MachineInstr & MI,unsigned Op) const226 unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op)
227 const { return 0; }
getT2AddrModeImm8OffsetOpValue(const MachineInstr & MI,unsigned Op) const228 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
229 const { return 0; }
getT2AddrModeImm12OffsetOpValue(const MachineInstr & MI,unsigned Op) const230 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
231 const { return 0; }
getT2AddrModeSORegOpValue(const MachineInstr & MI,unsigned Op) const232 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
233 const { return 0; }
getT2SORegOpValue(const MachineInstr & MI,unsigned Op) const234 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
235 const { return 0; }
getT2AdrLabelOpValue(const MachineInstr & MI,unsigned Op) const236 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
237 const { return 0; }
getAddrMode6AddressOpValue(const MachineInstr & MI,unsigned Op) const238 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
239 const { return 0; }
getAddrMode6OneLane32AddressOpValue(const MachineInstr & MI,unsigned Op) const240 unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI,
241 unsigned Op)
242 const { return 0; }
getAddrMode6DupAddressOpValue(const MachineInstr & MI,unsigned Op) const243 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
244 const { return 0; }
getAddrMode6OffsetOpValue(const MachineInstr & MI,unsigned Op) const245 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
246 const { return 0; }
getBitfieldInvertedMaskOpValue(const MachineInstr & MI,unsigned Op) const247 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
248 unsigned Op) const { return 0; }
getSsatBitPosValue(const MachineInstr & MI,unsigned Op) const249 unsigned getSsatBitPosValue(const MachineInstr &MI,
250 unsigned Op) const { return 0; }
getLdStmModeOpValue(const MachineInstr & MI,unsigned OpIdx) const251 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
252 const {return 0; }
getLdStSORegOpValue(const MachineInstr & MI,unsigned OpIdx) const253 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
254 const { return 0; }
255
getAddrModeImm12OpValue(const MachineInstr & MI,unsigned Op) const256 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
257 const {
258 // {17-13} = reg
259 // {12} = (U)nsigned (add == '1', sub == '0')
260 // {11-0} = imm12
261 const MachineOperand &MO = MI.getOperand(Op);
262 const MachineOperand &MO1 = MI.getOperand(Op + 1);
263 if (!MO.isReg()) {
264 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
265 return 0;
266 }
267 unsigned Reg = getARMRegisterNumbering(MO.getReg());
268 int32_t Imm12 = MO1.getImm();
269 uint32_t Binary;
270 Binary = Imm12 & 0xfff;
271 if (Imm12 >= 0)
272 Binary |= (1 << 12);
273 Binary |= (Reg << 13);
274 return Binary;
275 }
276
getHiLo16ImmOpValue(const MachineInstr & MI,unsigned Op) const277 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op)
278 const {
279 const MCInstrDesc &MCID = MI.getDesc();
280 const MachineOperand &MO = MI.getOperand(Op);
281
282 unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ?
283 ARM::reloc_arm_movw : ARM::reloc_arm_movt);
284
285 if (!MO.isImm()) {
286 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
287 return 0;
288 }
289 unsigned Imm16 = static_cast<unsigned>(MO.getImm());
290 return Imm16;
291 }
292
getAddrMode2OpValue(const MachineInstr & MI,unsigned OpIdx) const293 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
294 const { return 0;}
getAddrMode2OffsetOpValue(const MachineInstr & MI,unsigned OpIdx) const295 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
296 const { return 0;}
getPostIdxRegOpValue(const MachineInstr & MI,unsigned OpIdx) const297 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
298 const { return 0;}
getAddrMode3OffsetOpValue(const MachineInstr & MI,unsigned OpIdx) const299 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
300 const { return 0;}
getAddrMode3OpValue(const MachineInstr & MI,unsigned Op) const301 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
302 const { return 0; }
getAddrModeThumbSPOpValue(const MachineInstr & MI,unsigned Op) const303 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
304 const { return 0; }
getAddrModeSOpValue(const MachineInstr & MI,unsigned Op) const305 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
306 const { return 0; }
getAddrModeISOpValue(const MachineInstr & MI,unsigned Op) const307 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
308 const { return 0; }
getAddrModePCOpValue(const MachineInstr & MI,unsigned Op) const309 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
310 const { return 0; }
getAddrMode5OpValue(const MachineInstr & MI,unsigned Op) const311 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
312 // {12-9} = reg
313 // {8} = (U)nsigned (add == '1', sub == '0')
314 // {7-0} = imm8
315 uint32_t Binary = 0;
316 const MachineOperand &MO = MI.getOperand(Op);
317 uint32_t Reg = getMachineOpValue(MI, MO);
318 Binary |= (Reg << 9);
319
320 // If there is a non-zero immediate offset, encode it.
321 if (MO.isReg()) {
322 const MachineOperand &MO1 = MI.getOperand(Op + 1);
323 if (uint32_t ImmOffs = ARM_AM::getAM5Offset(MO1.getImm())) {
324 if (ARM_AM::getAM5Op(MO1.getImm()) == ARM_AM::add)
325 Binary |= 1 << 8;
326 Binary |= ImmOffs & 0xff;
327 return Binary;
328 }
329 }
330
331 // If immediate offset is omitted, default to +0.
332 Binary |= 1 << 8;
333 return Binary;
334 }
getNEONVcvtImm32OpValue(const MachineInstr & MI,unsigned Op) const335 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
336 const { return 0; }
337
getRegisterListOpValue(const MachineInstr & MI,unsigned Op) const338 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
339 const { return 0; }
340
getShiftRight8Imm(const MachineInstr & MI,unsigned Op) const341 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)
342 const { return 0; }
getShiftRight16Imm(const MachineInstr & MI,unsigned Op) const343 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)
344 const { return 0; }
getShiftRight32Imm(const MachineInstr & MI,unsigned Op) const345 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)
346 const { return 0; }
getShiftRight64Imm(const MachineInstr & MI,unsigned Op) const347 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)
348 const { return 0; }
349
350 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
351 /// machine operand requires relocation, record the relocation and return
352 /// zero.
353 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
354 unsigned Reloc);
355
356 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
357 ///
358 unsigned getShiftOp(unsigned Imm) const ;
359
360 /// Routines that handle operands which add machine relocations which are
361 /// fixed up by the relocation stage.
362 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
363 bool MayNeedFarStub, bool Indirect,
364 intptr_t ACPV = 0) const;
365 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
366 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
367 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
368 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
369 intptr_t JTBase = 0) const;
370 };
371 }
372
373 char ARMCodeEmitter::ID = 0;
374
375 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
376 /// code to the specified MCE object.
createARMJITCodeEmitterPass(ARMBaseTargetMachine & TM,JITCodeEmitter & JCE)377 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
378 JITCodeEmitter &JCE) {
379 return new ARMCodeEmitter(TM, JCE);
380 }
381
runOnMachineFunction(MachineFunction & MF)382 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
383 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
384 MF.getTarget().getRelocationModel() != Reloc::Static) &&
385 "JIT relocation model must be set to static or default!");
386 JTI = ((ARMBaseTargetMachine &)MF.getTarget()).getJITInfo();
387 II = (const ARMBaseInstrInfo *)MF.getTarget().getInstrInfo();
388 TD = MF.getTarget().getTargetData();
389 Subtarget = &TM.getSubtarget<ARMSubtarget>();
390 MCPEs = &MF.getConstantPool()->getConstants();
391 MJTEs = 0;
392 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
393 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
394 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
395 JTI->Initialize(MF, IsPIC);
396 MMI = &getAnalysis<MachineModuleInfo>();
397 MCE.setModuleInfo(MMI);
398
399 do {
400 DEBUG(errs() << "JITTing function '"
401 << MF.getFunction()->getName() << "'\n");
402 MCE.startFunction(MF);
403 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
404 MBB != E; ++MBB) {
405 MCE.StartMachineBasicBlock(MBB);
406 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
407 I != E; ++I)
408 emitInstruction(*I);
409 }
410 } while (MCE.finishFunction(MF));
411
412 return false;
413 }
414
415 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
416 ///
getShiftOp(unsigned Imm) const417 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
418 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
419 default: llvm_unreachable("Unknown shift opc!");
420 case ARM_AM::asr: return 2;
421 case ARM_AM::lsl: return 0;
422 case ARM_AM::lsr: return 1;
423 case ARM_AM::ror:
424 case ARM_AM::rrx: return 3;
425 }
426 }
427
428 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
429 /// machine operand requires relocation, record the relocation and return zero.
getMovi32Value(const MachineInstr & MI,const MachineOperand & MO,unsigned Reloc)430 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
431 const MachineOperand &MO,
432 unsigned Reloc) {
433 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
434 && "Relocation to this function should be for movt or movw");
435
436 if (MO.isImm())
437 return static_cast<unsigned>(MO.getImm());
438 else if (MO.isGlobal())
439 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
440 else if (MO.isSymbol())
441 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
442 else if (MO.isMBB())
443 emitMachineBasicBlock(MO.getMBB(), Reloc);
444 else {
445 #ifndef NDEBUG
446 errs() << MO;
447 #endif
448 llvm_unreachable("Unsupported operand type for movw/movt");
449 }
450 return 0;
451 }
452
453 /// getMachineOpValue - Return binary encoding of operand. If the machine
454 /// operand requires relocation, record the relocation and return zero.
getMachineOpValue(const MachineInstr & MI,const MachineOperand & MO) const455 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
456 const MachineOperand &MO) const {
457 if (MO.isReg())
458 return getARMRegisterNumbering(MO.getReg());
459 else if (MO.isImm())
460 return static_cast<unsigned>(MO.getImm());
461 else if (MO.isFPImm())
462 return static_cast<unsigned>(MO.getFPImm()->getValueAPF()
463 .bitcastToAPInt().getHiBits(32).getLimitedValue());
464 else if (MO.isGlobal())
465 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
466 else if (MO.isSymbol())
467 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
468 else if (MO.isCPI()) {
469 const MCInstrDesc &MCID = MI.getDesc();
470 // For VFP load, the immediate offset is multiplied by 4.
471 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
472 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
473 emitConstPoolAddress(MO.getIndex(), Reloc);
474 } else if (MO.isJTI())
475 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
476 else if (MO.isMBB())
477 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
478 else
479 llvm_unreachable("Unable to encode MachineOperand!");
480 return 0;
481 }
482
483 /// emitGlobalAddress - Emit the specified address to the code stream.
484 ///
emitGlobalAddress(const GlobalValue * GV,unsigned Reloc,bool MayNeedFarStub,bool Indirect,intptr_t ACPV) const485 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
486 bool MayNeedFarStub, bool Indirect,
487 intptr_t ACPV) const {
488 MachineRelocation MR = Indirect
489 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
490 const_cast<GlobalValue *>(GV),
491 ACPV, MayNeedFarStub)
492 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
493 const_cast<GlobalValue *>(GV), ACPV,
494 MayNeedFarStub);
495 MCE.addRelocation(MR);
496 }
497
498 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
499 /// be emitted to the current location in the function, and allow it to be PC
500 /// relative.
501 void ARMCodeEmitter::
emitExternalSymbolAddress(const char * ES,unsigned Reloc) const502 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
503 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
504 Reloc, ES));
505 }
506
507 /// emitConstPoolAddress - Arrange for the address of an constant pool
508 /// to be emitted to the current location in the function, and allow it to be PC
509 /// relative.
emitConstPoolAddress(unsigned CPI,unsigned Reloc) const510 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
511 // Tell JIT emitter we'll resolve the address.
512 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
513 Reloc, CPI, 0, true));
514 }
515
516 /// emitJumpTableAddress - Arrange for the address of a jump table to
517 /// be emitted to the current location in the function, and allow it to be PC
518 /// relative.
519 void ARMCodeEmitter::
emitJumpTableAddress(unsigned JTIndex,unsigned Reloc) const520 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
521 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
522 Reloc, JTIndex, 0, true));
523 }
524
525 /// emitMachineBasicBlock - Emit the specified address basic block.
emitMachineBasicBlock(MachineBasicBlock * BB,unsigned Reloc,intptr_t JTBase) const526 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
527 unsigned Reloc,
528 intptr_t JTBase) const {
529 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
530 Reloc, BB, JTBase));
531 }
532
emitWordLE(unsigned Binary)533 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
534 DEBUG(errs() << " 0x";
535 errs().write_hex(Binary) << "\n");
536 MCE.emitWordLE(Binary);
537 }
538
emitDWordLE(uint64_t Binary)539 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
540 DEBUG(errs() << " 0x";
541 errs().write_hex(Binary) << "\n");
542 MCE.emitDWordLE(Binary);
543 }
544
emitInstruction(const MachineInstr & MI)545 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
546 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
547
548 MCE.processDebugLoc(MI.getDebugLoc(), true);
549
550 ++NumEmitted; // Keep track of the # of mi's emitted
551 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
552 default: {
553 llvm_unreachable("Unhandled instruction encoding format!");
554 }
555 case ARMII::MiscFrm:
556 if (MI.getOpcode() == ARM::LEApcrelJT) {
557 // Materialize jumptable address.
558 emitLEApcrelJTInstruction(MI);
559 break;
560 }
561 llvm_unreachable("Unhandled instruction encoding!");
562 case ARMII::Pseudo:
563 emitPseudoInstruction(MI);
564 break;
565 case ARMII::DPFrm:
566 case ARMII::DPSoRegFrm:
567 emitDataProcessingInstruction(MI);
568 break;
569 case ARMII::LdFrm:
570 case ARMII::StFrm:
571 emitLoadStoreInstruction(MI);
572 break;
573 case ARMII::LdMiscFrm:
574 case ARMII::StMiscFrm:
575 emitMiscLoadStoreInstruction(MI);
576 break;
577 case ARMII::LdStMulFrm:
578 emitLoadStoreMultipleInstruction(MI);
579 break;
580 case ARMII::MulFrm:
581 emitMulFrmInstruction(MI);
582 break;
583 case ARMII::ExtFrm:
584 emitExtendInstruction(MI);
585 break;
586 case ARMII::ArithMiscFrm:
587 emitMiscArithInstruction(MI);
588 break;
589 case ARMII::SatFrm:
590 emitSaturateInstruction(MI);
591 break;
592 case ARMII::BrFrm:
593 emitBranchInstruction(MI);
594 break;
595 case ARMII::BrMiscFrm:
596 emitMiscBranchInstruction(MI);
597 break;
598 // VFP instructions.
599 case ARMII::VFPUnaryFrm:
600 case ARMII::VFPBinaryFrm:
601 emitVFPArithInstruction(MI);
602 break;
603 case ARMII::VFPConv1Frm:
604 case ARMII::VFPConv2Frm:
605 case ARMII::VFPConv3Frm:
606 case ARMII::VFPConv4Frm:
607 case ARMII::VFPConv5Frm:
608 emitVFPConversionInstruction(MI);
609 break;
610 case ARMII::VFPLdStFrm:
611 emitVFPLoadStoreInstruction(MI);
612 break;
613 case ARMII::VFPLdStMulFrm:
614 emitVFPLoadStoreMultipleInstruction(MI);
615 break;
616 case ARMII::VFPMiscFrm:
617 emitMiscInstruction(MI);
618 break;
619 // NEON instructions.
620 case ARMII::NGetLnFrm:
621 case ARMII::NSetLnFrm:
622 emitNEONLaneInstruction(MI);
623 break;
624 case ARMII::NDupFrm:
625 emitNEONDupInstruction(MI);
626 break;
627 case ARMII::N1RegModImmFrm:
628 emitNEON1RegModImmInstruction(MI);
629 break;
630 case ARMII::N2RegFrm:
631 emitNEON2RegInstruction(MI);
632 break;
633 case ARMII::N3RegFrm:
634 emitNEON3RegInstruction(MI);
635 break;
636 }
637 MCE.processDebugLoc(MI.getDebugLoc(), false);
638 }
639
emitConstantToMemory(unsigned CPI,const Constant * C)640 void ARMCodeEmitter::emitConstantToMemory(unsigned CPI, const Constant *C) {
641 DEBUG({
642 errs() << " ** Constant pool #" << CPI << " @ "
643 << (void*)MCE.getCurrentPCValue() << " ";
644 if (const Function *F = dyn_cast<Function>(C))
645 errs() << F->getName();
646 else
647 errs() << *C;
648 errs() << '\n';
649 });
650
651 switch (C->getValueID()) {
652 default: {
653 llvm_unreachable("Unable to handle this constantpool entry!");
654 break;
655 }
656 case Value::GlobalVariableVal: {
657 emitGlobalAddress(static_cast<const GlobalValue*>(C),
658 ARM::reloc_arm_absolute, isa<Function>(C), false);
659 emitWordLE(0);
660 break;
661 }
662 case Value::ConstantIntVal: {
663 const ConstantInt *CI = static_cast<const ConstantInt*>(C);
664 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
665 emitWordLE(Val);
666 break;
667 }
668 case Value::ConstantFPVal: {
669 const ConstantFP *CFP = static_cast<const ConstantFP*>(C);
670 if (CFP->getType()->isFloatTy())
671 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
672 else if (CFP->getType()->isDoubleTy())
673 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
674 else {
675 llvm_unreachable("Unable to handle this constantpool entry!");
676 }
677 break;
678 }
679 case Value::ConstantArrayVal: {
680 const ConstantArray *CA = static_cast<const ConstantArray*>(C);
681 for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i)
682 emitConstantToMemory(CPI, CA->getOperand(i));
683 break;
684 }
685 case Value::ConstantVectorVal:{
686 //FIXME:emit vector
687 const ConstantVector *CV = static_cast<const ConstantVector*>(C);
688 break;
689 }
690 }
691
692 return;
693 }
694
emitConstPoolInstruction(const MachineInstr & MI)695 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
696 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
697 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
698 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
699
700 // Remember the CONSTPOOL_ENTRY address for later relocation.
701 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
702
703 // Emit constpool island entry. In most cases, the actual values will be
704 // resolved and relocated after code emission.
705 if (MCPE.isMachineConstantPoolEntry()) {
706 ARMConstantPoolValue *ACPV =
707 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
708
709 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
710 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
711
712 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
713 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
714 if (GV) {
715 Reloc::Model RelocM = TM.getRelocationModel();
716 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
717 isa<Function>(GV),
718 Subtarget->GVIsIndirectSymbol(GV, RelocM),
719 (intptr_t)ACPV);
720 } else {
721 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
722 emitExternalSymbolAddress(Sym, ARM::reloc_arm_absolute);
723 }
724 emitWordLE(0);
725 } else {
726 emitConstantToMemory(CPI, MCPE.Val.ConstVal);
727 }
728 }
729
emitMOVi32immInstruction(const MachineInstr & MI)730 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
731 const MachineOperand &MO0 = MI.getOperand(0);
732 const MachineOperand &MO1 = MI.getOperand(1);
733
734 // Emit the 'movw' instruction.
735 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
736
737 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
738
739 // Set the conditional execution predicate.
740 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
741
742 // Encode Rd.
743 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
744
745 // Encode imm16 as imm4:imm12
746 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
747 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
748 emitWordLE(Binary);
749
750 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
751 // Emit the 'movt' instruction.
752 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
753
754 // Set the conditional execution predicate.
755 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
756
757 // Encode Rd.
758 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
759
760 // Encode imm16 as imm4:imm1, same as movw above.
761 Binary |= Hi16 & 0xFFF;
762 Binary |= ((Hi16 >> 12) & 0xF) << 16;
763 emitWordLE(Binary);
764 }
765
emitMOVi2piecesInstruction(const MachineInstr & MI)766 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
767 const MachineOperand &MO0 = MI.getOperand(0);
768 const MachineOperand &MO1 = MI.getOperand(1);
769 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
770 "Not a valid so_imm value!");
771 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
772 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
773
774 // Emit the 'mov' instruction.
775 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
776
777 // Set the conditional execution predicate.
778 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
779
780 // Encode Rd.
781 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
782
783 // Encode so_imm.
784 // Set bit I(25) to identify this is the immediate form of <shifter_op>
785 Binary |= 1 << ARMII::I_BitShift;
786 Binary |= getMachineSoImmOpValue(V1);
787 emitWordLE(Binary);
788
789 // Now the 'orr' instruction.
790 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
791
792 // Set the conditional execution predicate.
793 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
794
795 // Encode Rd.
796 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
797
798 // Encode Rn.
799 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
800
801 // Encode so_imm.
802 // Set bit I(25) to identify this is the immediate form of <shifter_op>
803 Binary |= 1 << ARMII::I_BitShift;
804 Binary |= getMachineSoImmOpValue(V2);
805 emitWordLE(Binary);
806 }
807
emitLEApcrelInstruction(const MachineInstr & MI)808 void ARMCodeEmitter::emitLEApcrelInstruction(const MachineInstr &MI) {
809 // It's basically add r, pc, (LCPI - $+8)
810 const MCInstrDesc &MCID = MI.getDesc();
811
812 unsigned Binary = 0;
813
814 // Set the conditional execution predicate
815 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
816
817 // Encode S bit if MI modifies CPSR.
818 Binary |= getAddrModeSBit(MI, MCID);
819
820 // Encode Rd.
821 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
822
823 // Encode Rn which is PC.
824 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
825
826 // Encode the displacement which is a so_imm.
827 // Set bit I(25) to identify this is the immediate form of <shifter_op>
828 Binary |= 1 << ARMII::I_BitShift;
829 emitConstPoolAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_so_imm_cp_entry);
830
831 emitWordLE(Binary);
832 }
833
emitLEApcrelJTInstruction(const MachineInstr & MI)834 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
835 // It's basically add r, pc, (LJTI - $+8)
836
837 const MCInstrDesc &MCID = MI.getDesc();
838
839 // Emit the 'add' instruction.
840 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100
841
842 // Set the conditional execution predicate
843 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
844
845 // Encode S bit if MI modifies CPSR.
846 Binary |= getAddrModeSBit(MI, MCID);
847
848 // Encode Rd.
849 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
850
851 // Encode Rn which is PC.
852 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
853
854 // Encode the displacement.
855 Binary |= 1 << ARMII::I_BitShift;
856 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
857
858 emitWordLE(Binary);
859 }
860
emitPseudoMoveInstruction(const MachineInstr & MI)861 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
862 unsigned Opcode = MI.getDesc().Opcode;
863
864 // Part of binary is determined by TableGn.
865 unsigned Binary = getBinaryCodeForInstr(MI);
866
867 // Set the conditional execution predicate
868 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
869
870 // Encode S bit if MI modifies CPSR.
871 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
872 Binary |= 1 << ARMII::S_BitShift;
873
874 // Encode register def if there is one.
875 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
876
877 // Encode the shift operation.
878 switch (Opcode) {
879 default: break;
880 case ARM::RRX:
881 // rrx
882 Binary |= 0x6 << 4;
883 break;
884 case ARM::MOVsrl_flag:
885 // lsr #1
886 Binary |= (0x2 << 4) | (1 << 7);
887 break;
888 case ARM::MOVsra_flag:
889 // asr #1
890 Binary |= (0x4 << 4) | (1 << 7);
891 break;
892 }
893
894 // Encode register Rm.
895 Binary |= getMachineOpValue(MI, 1);
896
897 emitWordLE(Binary);
898 }
899
addPCLabel(unsigned LabelID)900 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
901 DEBUG(errs() << " ** LPC" << LabelID << " @ "
902 << (void*)MCE.getCurrentPCValue() << '\n');
903 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
904 }
905
emitPseudoInstruction(const MachineInstr & MI)906 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
907 unsigned Opcode = MI.getDesc().Opcode;
908 switch (Opcode) {
909 default:
910 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
911 case ARM::B:
912 emitBranchInstruction(MI);
913 break;
914 case ARM::BR_JTr:
915 case ARM::BR_JTm:
916 case ARM::BR_JTadd:
917 emitMiscBranchInstruction(MI);
918 break;
919 case ARM::BX_CALL:
920 case ARM::BMOVPCRX_CALL: {
921 // First emit mov lr, pc
922 unsigned Binary = 0x01a0e00f;
923 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
924 emitWordLE(Binary);
925
926 // and then emit the branch.
927 emitMiscBranchInstruction(MI);
928 break;
929 }
930 case TargetOpcode::INLINEASM: {
931 // We allow inline assembler nodes with empty bodies - they can
932 // implicitly define registers, which is ok for JIT.
933 if (MI.getOperand(0).getSymbolName()[0]) {
934 report_fatal_error("JIT does not support inline asm!");
935 }
936 break;
937 }
938 case TargetOpcode::PROLOG_LABEL:
939 case TargetOpcode::EH_LABEL:
940 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
941 break;
942 case TargetOpcode::IMPLICIT_DEF:
943 case TargetOpcode::KILL:
944 // Do nothing.
945 break;
946 case ARM::CONSTPOOL_ENTRY:
947 emitConstPoolInstruction(MI);
948 break;
949 case ARM::LDMIA_RET:
950 emitLoadStoreMultipleInstruction(MI);
951 break;
952 case ARM::PICADD: {
953 // Remember of the address of the PC label for relocation later.
954 addPCLabel(MI.getOperand(2).getImm());
955 // PICADD is just an add instruction that implicitly read pc.
956 emitDataProcessingInstruction(MI, 0, ARM::PC);
957 break;
958 }
959 case ARM::PICLDR:
960 case ARM::PICLDRB:
961 case ARM::PICSTR:
962 case ARM::PICSTRB: {
963 // Remember of the address of the PC label for relocation later.
964 addPCLabel(MI.getOperand(2).getImm());
965 // These are just load / store instructions that implicitly read pc.
966 emitLoadStoreInstruction(MI, 0, ARM::PC);
967 break;
968 }
969 case ARM::PICLDRH:
970 case ARM::PICLDRSH:
971 case ARM::PICLDRSB:
972 case ARM::PICSTRH: {
973 // Remember of the address of the PC label for relocation later.
974 addPCLabel(MI.getOperand(2).getImm());
975 // These are just load / store instructions that implicitly read pc.
976 emitMiscLoadStoreInstruction(MI, ARM::PC);
977 break;
978 }
979
980 case ARM::MOVi32imm:
981 // Two instructions to materialize a constant.
982 if (Subtarget->hasV6T2Ops())
983 emitMOVi32immInstruction(MI);
984 else
985 emitMOVi2piecesInstruction(MI);
986 break;
987 case ARM::LEApcrel:
988 // Materialize constantpool index address.
989 emitLEApcrelInstruction(MI);
990 break;
991 case ARM::LEApcrelJT:
992 // Materialize jumptable address.
993 emitLEApcrelJTInstruction(MI);
994 break;
995 case ARM::RRX:
996 case ARM::MOVsrl_flag:
997 case ARM::MOVsra_flag:
998 emitPseudoMoveInstruction(MI);
999 break;
1000 }
1001 }
1002
getMachineSoRegOpValue(const MachineInstr & MI,const MCInstrDesc & MCID,const MachineOperand & MO,unsigned OpIdx)1003 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
1004 const MCInstrDesc &MCID,
1005 const MachineOperand &MO,
1006 unsigned OpIdx) {
1007 unsigned Binary = getMachineOpValue(MI, MO);
1008
1009 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
1010 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
1011 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1012
1013 // Encode the shift opcode.
1014 unsigned SBits = 0;
1015 unsigned Rs = MO1.getReg();
1016 if (Rs) {
1017 // Set shift operand (bit[7:4]).
1018 // LSL - 0001
1019 // LSR - 0011
1020 // ASR - 0101
1021 // ROR - 0111
1022 // RRX - 0110 and bit[11:8] clear.
1023 switch (SOpc) {
1024 default: llvm_unreachable("Unknown shift opc!");
1025 case ARM_AM::lsl: SBits = 0x1; break;
1026 case ARM_AM::lsr: SBits = 0x3; break;
1027 case ARM_AM::asr: SBits = 0x5; break;
1028 case ARM_AM::ror: SBits = 0x7; break;
1029 case ARM_AM::rrx: SBits = 0x6; break;
1030 }
1031 } else {
1032 // Set shift operand (bit[6:4]).
1033 // LSL - 000
1034 // LSR - 010
1035 // ASR - 100
1036 // ROR - 110
1037 switch (SOpc) {
1038 default: llvm_unreachable("Unknown shift opc!");
1039 case ARM_AM::lsl: SBits = 0x0; break;
1040 case ARM_AM::lsr: SBits = 0x2; break;
1041 case ARM_AM::asr: SBits = 0x4; break;
1042 case ARM_AM::ror: SBits = 0x6; break;
1043 }
1044 }
1045 Binary |= SBits << 4;
1046 if (SOpc == ARM_AM::rrx)
1047 return Binary;
1048
1049 // Encode the shift operation Rs or shift_imm (except rrx).
1050 if (Rs) {
1051 // Encode Rs bit[11:8].
1052 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1053 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
1054 }
1055
1056 // Encode shift_imm bit[11:7].
1057 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
1058 }
1059
getMachineSoImmOpValue(unsigned SoImm)1060 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
1061 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
1062 assert(SoImmVal != -1 && "Not a valid so_imm value!");
1063
1064 // Encode rotate_imm.
1065 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
1066 << ARMII::SoRotImmShift;
1067
1068 // Encode immed_8.
1069 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
1070 return Binary;
1071 }
1072
getAddrModeSBit(const MachineInstr & MI,const MCInstrDesc & MCID) const1073 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
1074 const MCInstrDesc &MCID) const {
1075 for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){
1076 const MachineOperand &MO = MI.getOperand(i-1);
1077 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
1078 return 1 << ARMII::S_BitShift;
1079 }
1080 return 0;
1081 }
1082
emitDataProcessingInstruction(const MachineInstr & MI,unsigned ImplicitRd,unsigned ImplicitRn)1083 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
1084 unsigned ImplicitRd,
1085 unsigned ImplicitRn) {
1086 const MCInstrDesc &MCID = MI.getDesc();
1087
1088 // Part of binary is determined by TableGn.
1089 unsigned Binary = getBinaryCodeForInstr(MI);
1090
1091 if (MCID.Opcode == ARM::MOVi16 || MCID.Opcode == ARM::MOVTi16) {
1092 emitWordLE(Binary);
1093 return;
1094 }
1095
1096 // Set the conditional execution predicate
1097 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1098
1099 // Encode S bit if MI modifies CPSR.
1100 Binary |= getAddrModeSBit(MI, MCID);
1101
1102 // Encode register def if there is one.
1103 unsigned NumDefs = MCID.getNumDefs();
1104 unsigned OpIdx = 0;
1105 if (NumDefs)
1106 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1107 else if (ImplicitRd)
1108 // Special handling for implicit use (e.g. PC).
1109 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1110
1111 if (MCID.Opcode == ARM::MOVi16) {
1112 // Get immediate from MI.
1113 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1114 ARM::reloc_arm_movw);
1115 // Encode imm which is the same as in emitMOVi32immInstruction().
1116 Binary |= Lo16 & 0xFFF;
1117 Binary |= ((Lo16 >> 12) & 0xF) << 16;
1118 emitWordLE(Binary);
1119 return;
1120 } else if(MCID.Opcode == ARM::MOVTi16) {
1121 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1122 ARM::reloc_arm_movt) >> 16);
1123 Binary |= Hi16 & 0xFFF;
1124 Binary |= ((Hi16 >> 12) & 0xF) << 16;
1125 emitWordLE(Binary);
1126 return;
1127 } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) {
1128 uint32_t v = ~MI.getOperand(2).getImm();
1129 int32_t lsb = CountTrailingZeros_32(v);
1130 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
1131 // Instr{20-16} = msb, Instr{11-7} = lsb
1132 Binary |= (msb & 0x1F) << 16;
1133 Binary |= (lsb & 0x1F) << 7;
1134 emitWordLE(Binary);
1135 return;
1136 } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) {
1137 // Encode Rn in Instr{0-3}
1138 Binary |= getMachineOpValue(MI, OpIdx++);
1139
1140 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1141 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1142
1143 // Instr{20-16} = widthm1, Instr{11-7} = lsb
1144 Binary |= (widthm1 & 0x1F) << 16;
1145 Binary |= (lsb & 0x1F) << 7;
1146 emitWordLE(Binary);
1147 return;
1148 }
1149
1150 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1151 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1152 ++OpIdx;
1153
1154 // Encode first non-shifter register operand if there is one.
1155 bool isUnary = MCID.TSFlags & ARMII::UnaryDP;
1156 if (!isUnary) {
1157 if (ImplicitRn)
1158 // Special handling for implicit use (e.g. PC).
1159 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1160 else {
1161 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1162 ++OpIdx;
1163 }
1164 }
1165
1166 // Encode shifter operand.
1167 const MachineOperand &MO = MI.getOperand(OpIdx);
1168 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1169 // Encode SoReg.
1170 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx));
1171 return;
1172 }
1173
1174 if (MO.isReg()) {
1175 // Encode register Rm.
1176 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1177 return;
1178 }
1179
1180 // Encode so_imm.
1181 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1182
1183 emitWordLE(Binary);
1184 }
1185
emitLoadStoreInstruction(const MachineInstr & MI,unsigned ImplicitRd,unsigned ImplicitRn)1186 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1187 unsigned ImplicitRd,
1188 unsigned ImplicitRn) {
1189 const MCInstrDesc &MCID = MI.getDesc();
1190 unsigned Form = MCID.TSFlags & ARMII::FormMask;
1191 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1192
1193 // Part of binary is determined by TableGn.
1194 unsigned Binary = getBinaryCodeForInstr(MI);
1195
1196 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1197 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1198 MI.getOpcode() == ARM::STRi12 || MI.getOpcode() == ARM::LDRBi12 ||
1199 MI.getOpcode() == ARM::STRBi12) {
1200 emitWordLE(Binary);
1201 return;
1202 }
1203
1204 if (MI.getOpcode() == ARM::BR_JTm)
1205 Binary = 0x710F000;
1206 else if (MI.getOpcode() == ARM::BR_JTr)
1207 Binary = 0x1A0F000;
1208
1209 // Set the conditional execution predicate
1210 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1211
1212 unsigned OpIdx = 0;
1213
1214 // Operand 0 of a pre- and post-indexed store is the address base
1215 // writeback. Skip it.
1216 bool Skipped = false;
1217 if (IsPrePost && Form == ARMII::StFrm) {
1218 ++OpIdx;
1219 Skipped = true;
1220 }
1221
1222 // Set first operand
1223 if (ImplicitRd)
1224 // Special handling for implicit use (e.g. PC).
1225 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1226 else
1227 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1228
1229 // Set second operand
1230 if (ImplicitRn)
1231 // Special handling for implicit use (e.g. PC).
1232 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1233 else
1234 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1235
1236 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1237 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1238 ++OpIdx;
1239
1240 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1241 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1242 ? 0 : MI.getOperand(OpIdx+1).getImm();
1243
1244 // Set bit U(23) according to sign of immed value (positive or negative).
1245 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1246 ARMII::U_BitShift);
1247 if (!MO2.getReg()) { // is immediate
1248 if (ARM_AM::getAM2Offset(AM2Opc))
1249 // Set the value of offset_12 field
1250 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1251 emitWordLE(Binary);
1252 return;
1253 }
1254
1255 // Set bit I(25), because this is not in immediate encoding.
1256 Binary |= 1 << ARMII::I_BitShift;
1257 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1258 // Set bit[3:0] to the corresponding Rm register
1259 Binary |= getARMRegisterNumbering(MO2.getReg());
1260
1261 // If this instr is in scaled register offset/index instruction, set
1262 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1263 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1264 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1265 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1266 }
1267
1268 emitWordLE(Binary);
1269 }
1270
emitMiscLoadStoreInstruction(const MachineInstr & MI,unsigned ImplicitRn)1271 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1272 unsigned ImplicitRn) {
1273 const MCInstrDesc &MCID = MI.getDesc();
1274 unsigned Form = MCID.TSFlags & ARMII::FormMask;
1275 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1276
1277 // Part of binary is determined by TableGn.
1278 unsigned Binary = getBinaryCodeForInstr(MI);
1279
1280 // Set the conditional execution predicate
1281 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1282
1283 unsigned OpIdx = 0;
1284
1285 // Operand 0 of a pre- and post-indexed store is the address base
1286 // writeback. Skip it.
1287 bool Skipped = false;
1288 if (IsPrePost && Form == ARMII::StMiscFrm) {
1289 ++OpIdx;
1290 Skipped = true;
1291 }
1292
1293 // Set first operand
1294 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1295
1296 // Skip LDRD and STRD's second operand.
1297 if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD)
1298 ++OpIdx;
1299
1300 // Set second operand
1301 if (ImplicitRn)
1302 // Special handling for implicit use (e.g. PC).
1303 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1304 else
1305 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1306
1307 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1308 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1309 ++OpIdx;
1310
1311 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1312 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1313 ? 0 : MI.getOperand(OpIdx+1).getImm();
1314
1315 // Set bit U(23) according to sign of immed value (positive or negative)
1316 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1317 ARMII::U_BitShift);
1318
1319 // If this instr is in register offset/index encoding, set bit[3:0]
1320 // to the corresponding Rm register.
1321 if (MO2.getReg()) {
1322 Binary |= getARMRegisterNumbering(MO2.getReg());
1323 emitWordLE(Binary);
1324 return;
1325 }
1326
1327 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1328 Binary |= 1 << ARMII::AM3_I_BitShift;
1329 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1330 // Set operands
1331 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1332 Binary |= (ImmOffs & 0xF); // immedL
1333 }
1334
1335 emitWordLE(Binary);
1336 }
1337
getAddrModeUPBits(unsigned Mode)1338 static unsigned getAddrModeUPBits(unsigned Mode) {
1339 unsigned Binary = 0;
1340
1341 // Set addressing mode by modifying bits U(23) and P(24)
1342 // IA - Increment after - bit U = 1 and bit P = 0
1343 // IB - Increment before - bit U = 1 and bit P = 1
1344 // DA - Decrement after - bit U = 0 and bit P = 0
1345 // DB - Decrement before - bit U = 0 and bit P = 1
1346 switch (Mode) {
1347 default: llvm_unreachable("Unknown addressing sub-mode!");
1348 case ARM_AM::da: break;
1349 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1350 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1351 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1352 }
1353
1354 return Binary;
1355 }
1356
emitLoadStoreMultipleInstruction(const MachineInstr & MI)1357 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1358 const MCInstrDesc &MCID = MI.getDesc();
1359 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1360
1361 // Part of binary is determined by TableGn.
1362 unsigned Binary = getBinaryCodeForInstr(MI);
1363
1364 if (MCID.getOpcode() == ARM::LDMIA_RET) {
1365 IsUpdating = true;
1366 Binary |= 0x8B00000;
1367 }
1368
1369 // Set the conditional execution predicate
1370 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1371
1372 // Skip operand 0 of an instruction with base register update.
1373 unsigned OpIdx = 0;
1374 if (IsUpdating)
1375 ++OpIdx;
1376
1377 // Set base address operand
1378 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1379
1380 // Set addressing mode by modifying bits U(23) and P(24)
1381 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1382 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1383
1384 // Set bit W(21)
1385 if (IsUpdating)
1386 Binary |= 0x1 << ARMII::W_BitShift;
1387
1388 // Set registers
1389 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1390 const MachineOperand &MO = MI.getOperand(i);
1391 if (!MO.isReg() || MO.isImplicit())
1392 break;
1393 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1394 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1395 RegNum < 16);
1396 Binary |= 0x1 << RegNum;
1397 }
1398
1399 emitWordLE(Binary);
1400 }
1401
emitMulFrmInstruction(const MachineInstr & MI)1402 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1403 const MCInstrDesc &MCID = MI.getDesc();
1404
1405 // Part of binary is determined by TableGn.
1406 unsigned Binary = getBinaryCodeForInstr(MI);
1407
1408 // Set the conditional execution predicate
1409 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1410
1411 // Encode S bit if MI modifies CPSR.
1412 Binary |= getAddrModeSBit(MI, MCID);
1413
1414 // 32x32->64bit operations have two destination registers. The number
1415 // of register definitions will tell us if that's what we're dealing with.
1416 unsigned OpIdx = 0;
1417 if (MCID.getNumDefs() == 2)
1418 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1419
1420 // Encode Rd
1421 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1422
1423 // Encode Rm
1424 Binary |= getMachineOpValue(MI, OpIdx++);
1425
1426 // Encode Rs
1427 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1428
1429 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1430 // it as Rn (for multiply, that's in the same offset as RdLo.
1431 if (MCID.getNumOperands() > OpIdx &&
1432 !MCID.OpInfo[OpIdx].isPredicate() &&
1433 !MCID.OpInfo[OpIdx].isOptionalDef())
1434 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1435
1436 emitWordLE(Binary);
1437 }
1438
emitExtendInstruction(const MachineInstr & MI)1439 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1440 const MCInstrDesc &MCID = MI.getDesc();
1441
1442 // Part of binary is determined by TableGn.
1443 unsigned Binary = getBinaryCodeForInstr(MI);
1444
1445 // Set the conditional execution predicate
1446 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1447
1448 unsigned OpIdx = 0;
1449
1450 // Encode Rd
1451 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1452
1453 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1454 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1455 if (MO2.isReg()) {
1456 // Two register operand form.
1457 // Encode Rn.
1458 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1459
1460 // Encode Rm.
1461 Binary |= getMachineOpValue(MI, MO2);
1462 ++OpIdx;
1463 } else {
1464 Binary |= getMachineOpValue(MI, MO1);
1465 }
1466
1467 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1468 if (MI.getOperand(OpIdx).isImm() &&
1469 !MCID.OpInfo[OpIdx].isPredicate() &&
1470 !MCID.OpInfo[OpIdx].isOptionalDef())
1471 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1472
1473 emitWordLE(Binary);
1474 }
1475
emitMiscArithInstruction(const MachineInstr & MI)1476 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1477 const MCInstrDesc &MCID = MI.getDesc();
1478
1479 // Part of binary is determined by TableGn.
1480 unsigned Binary = getBinaryCodeForInstr(MI);
1481
1482 // Set the conditional execution predicate
1483 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1484
1485 // PKH instructions are finished at this point
1486 if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) {
1487 emitWordLE(Binary);
1488 return;
1489 }
1490
1491 unsigned OpIdx = 0;
1492
1493 // Encode Rd
1494 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1495
1496 const MachineOperand &MO = MI.getOperand(OpIdx++);
1497 if (OpIdx == MCID.getNumOperands() ||
1498 MCID.OpInfo[OpIdx].isPredicate() ||
1499 MCID.OpInfo[OpIdx].isOptionalDef()) {
1500 // Encode Rm and it's done.
1501 Binary |= getMachineOpValue(MI, MO);
1502 emitWordLE(Binary);
1503 return;
1504 }
1505
1506 // Encode Rn.
1507 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1508
1509 // Encode Rm.
1510 Binary |= getMachineOpValue(MI, OpIdx++);
1511
1512 // Encode shift_imm.
1513 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1514 if (MCID.Opcode == ARM::PKHTB) {
1515 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1516 if (ShiftAmt == 32)
1517 ShiftAmt = 0;
1518 }
1519 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1520 Binary |= ShiftAmt << ARMII::ShiftShift;
1521
1522 emitWordLE(Binary);
1523 }
1524
emitSaturateInstruction(const MachineInstr & MI)1525 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1526 const MCInstrDesc &MCID = MI.getDesc();
1527
1528 // Part of binary is determined by TableGen.
1529 unsigned Binary = getBinaryCodeForInstr(MI);
1530
1531 // Set the conditional execution predicate
1532 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1533
1534 // Encode Rd
1535 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1536
1537 // Encode saturate bit position.
1538 unsigned Pos = MI.getOperand(1).getImm();
1539 if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16)
1540 Pos -= 1;
1541 assert((Pos < 16 || (Pos < 32 &&
1542 MCID.Opcode != ARM::SSAT16 &&
1543 MCID.Opcode != ARM::USAT16)) &&
1544 "saturate bit position out of range");
1545 Binary |= Pos << 16;
1546
1547 // Encode Rm
1548 Binary |= getMachineOpValue(MI, 2);
1549
1550 // Encode shift_imm.
1551 if (MCID.getNumOperands() == 4) {
1552 unsigned ShiftOp = MI.getOperand(3).getImm();
1553 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1554 if (Opc == ARM_AM::asr)
1555 Binary |= (1 << 6);
1556 unsigned ShiftAmt = MI.getOperand(3).getImm();
1557 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1558 ShiftAmt = 0;
1559 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1560 Binary |= ShiftAmt << ARMII::ShiftShift;
1561 }
1562
1563 emitWordLE(Binary);
1564 }
1565
emitBranchInstruction(const MachineInstr & MI)1566 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1567 const MCInstrDesc &MCID = MI.getDesc();
1568
1569 if (MCID.Opcode == ARM::TPsoft) {
1570 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1571 }
1572
1573 // Part of binary is determined by TableGn.
1574 unsigned Binary = getBinaryCodeForInstr(MI);
1575
1576 if (MCID.Opcode == ARM::B) {
1577 Binary = 0xEA000000;
1578 }
1579
1580 // Set the conditional execution predicate
1581 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1582
1583 // Set signed_immed_24 field
1584 Binary |= getMachineOpValue(MI, 0);
1585
1586 emitWordLE(Binary);
1587 }
1588
emitInlineJumpTable(unsigned JTIndex)1589 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1590 // Remember the base address of the inline jump table.
1591 uintptr_t JTBase = MCE.getCurrentPCValue();
1592 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1593 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1594 << '\n');
1595
1596 // Now emit the jump table entries.
1597 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1598 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1599 if (IsPIC)
1600 // DestBB address - JT base.
1601 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1602 else
1603 // Absolute DestBB address.
1604 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1605 emitWordLE(0);
1606 }
1607 }
1608
emitMiscBranchInstruction(const MachineInstr & MI)1609 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1610 const MCInstrDesc &MCID = MI.getDesc();
1611
1612 // Handle jump tables.
1613 if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) {
1614 // First emit a ldr pc, [] instruction.
1615 emitDataProcessingInstruction(MI, ARM::PC);
1616
1617 // Then emit the inline jump table.
1618 unsigned JTIndex =
1619 (MCID.Opcode == ARM::BR_JTr)
1620 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1621 emitInlineJumpTable(JTIndex);
1622 return;
1623 } else if (MCID.Opcode == ARM::BR_JTm) {
1624 // First emit a ldr pc, [] instruction.
1625 emitLoadStoreInstruction(MI, ARM::PC);
1626
1627 // Then emit the inline jump table.
1628 emitInlineJumpTable(MI.getOperand(3).getIndex());
1629 return;
1630 }
1631
1632 // Part of binary is determined by TableGn.
1633 unsigned Binary = getBinaryCodeForInstr(MI);
1634
1635 // Set the conditional execution predicate
1636 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1637
1638 if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR)
1639 // The return register is LR.
1640 Binary |= getARMRegisterNumbering(ARM::LR);
1641 else
1642 // otherwise, set the return register
1643 Binary |= getMachineOpValue(MI, 0);
1644
1645 emitWordLE(Binary);
1646 }
1647
encodeVFPRd(const MachineInstr & MI,unsigned OpIdx)1648 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1649 unsigned RegD = MI.getOperand(OpIdx).getReg();
1650 unsigned Binary = 0;
1651 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1652 RegD = getARMRegisterNumbering(RegD);
1653 if (!isSPVFP) {
1654 Binary |= (RegD & 0x0F) << ARMII::RegRdShift;
1655 Binary |= ((RegD & 0x10) >> 4) << ARMII::D_BitShift;
1656 } else {
1657 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1658 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1659 }
1660 return Binary;
1661 }
1662
encodeVFPRn(const MachineInstr & MI,unsigned OpIdx)1663 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1664 unsigned RegN = MI.getOperand(OpIdx).getReg();
1665 unsigned Binary = 0;
1666 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1667 RegN = getARMRegisterNumbering(RegN);
1668 if (!isSPVFP) {
1669 Binary |= (RegN & 0x0F) << ARMII::RegRnShift;
1670 Binary |= ((RegN & 0x10) >> 4) << ARMII::N_BitShift;
1671 } else {
1672 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1673 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1674 }
1675 return Binary;
1676 }
1677
encodeVFPRm(const MachineInstr & MI,unsigned OpIdx)1678 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1679 unsigned RegM = MI.getOperand(OpIdx).getReg();
1680 unsigned Binary = 0;
1681 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1682 RegM = getARMRegisterNumbering(RegM);
1683 if (!isSPVFP) {
1684 Binary |= (RegM & 0x0F);
1685 Binary |= ((RegM & 0x10) >> 4) << ARMII::M_BitShift;
1686 } else {
1687 Binary |= ((RegM & 0x1E) >> 1);
1688 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1689 }
1690 return Binary;
1691 }
1692
emitVFPArithInstruction(const MachineInstr & MI)1693 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1694 const MCInstrDesc &MCID = MI.getDesc();
1695
1696 // Part of binary is determined by TableGn.
1697 unsigned Binary = getBinaryCodeForInstr(MI);
1698
1699 // Set the conditional execution predicate
1700 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1701
1702 unsigned OpIdx = 0;
1703
1704 // Encode Dd / Sd.
1705 Binary |= encodeVFPRd(MI, OpIdx++);
1706
1707 // If this is a two-address operand, skip it, e.g. FMACD.
1708 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1709 ++OpIdx;
1710
1711 // Encode Dn / Sn.
1712 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1713 Binary |= encodeVFPRn(MI, OpIdx++);
1714
1715 if (OpIdx == MCID.getNumOperands() ||
1716 MCID.OpInfo[OpIdx].isPredicate() ||
1717 MCID.OpInfo[OpIdx].isOptionalDef()) {
1718 // FCMPEZD etc. has only one operand.
1719 emitWordLE(Binary);
1720 return;
1721 }
1722
1723 // Encode Dm / Sm.
1724 Binary |= encodeVFPRm(MI, OpIdx);
1725
1726 emitWordLE(Binary);
1727 }
1728
emitVFPConversionInstruction(const MachineInstr & MI)1729 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1730 const MCInstrDesc &MCID = MI.getDesc();
1731 unsigned Form = MCID.TSFlags & ARMII::FormMask;
1732
1733 // Part of binary is determined by TableGn.
1734 unsigned Binary = getBinaryCodeForInstr(MI);
1735
1736 // Set the conditional execution predicate
1737 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1738
1739 switch (Form) {
1740 default: break;
1741 case ARMII::VFPConv1Frm:
1742 case ARMII::VFPConv2Frm:
1743 case ARMII::VFPConv3Frm:
1744 // Encode Dd / Sd.
1745 Binary |= encodeVFPRd(MI, 0);
1746 break;
1747 case ARMII::VFPConv4Frm:
1748 // Encode Dn / Sn.
1749 Binary |= encodeVFPRn(MI, 0);
1750 break;
1751 case ARMII::VFPConv5Frm:
1752 // Encode Dm / Sm.
1753 Binary |= encodeVFPRm(MI, 0);
1754 break;
1755 }
1756
1757 switch (Form) {
1758 default: break;
1759 case ARMII::VFPConv1Frm:
1760 // Encode Dm / Sm.
1761 Binary |= encodeVFPRm(MI, 1);
1762 break;
1763 case ARMII::VFPConv2Frm:
1764 case ARMII::VFPConv3Frm:
1765 // Encode Dn / Sn.
1766 Binary |= encodeVFPRn(MI, 1);
1767 break;
1768 case ARMII::VFPConv4Frm:
1769 case ARMII::VFPConv5Frm:
1770 // Encode Dd / Sd.
1771 Binary |= encodeVFPRd(MI, 1);
1772 break;
1773 }
1774
1775 if (Form == ARMII::VFPConv5Frm)
1776 // Encode Dn / Sn.
1777 Binary |= encodeVFPRn(MI, 2);
1778 else if (Form == ARMII::VFPConv3Frm)
1779 // Encode Dm / Sm.
1780 Binary |= encodeVFPRm(MI, 2);
1781
1782 emitWordLE(Binary);
1783 }
1784
emitVFPLoadStoreInstruction(const MachineInstr & MI)1785 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1786 // Part of binary is determined by TableGn.
1787 unsigned Binary = getBinaryCodeForInstr(MI);
1788
1789 // Set the conditional execution predicate
1790 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1791
1792 if (MI.getOpcode() == ARM::VLDRS || MI.getOpcode() == ARM::VLDRD ||
1793 MI.getOpcode() == ARM::VSTRS || MI.getOpcode() == ARM::VSTRD){
1794 emitWordLE(Binary);
1795 return;
1796 }
1797
1798 unsigned OpIdx = 0;
1799
1800 // Encode Dd / Sd.
1801 Binary |= encodeVFPRd(MI, OpIdx++);
1802
1803 // Encode address base.
1804 const MachineOperand &Base = MI.getOperand(OpIdx++);
1805 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1806
1807 // If there is a non-zero immediate offset, encode it.
1808 if (Base.isReg()) {
1809 const MachineOperand &Offset = MI.getOperand(OpIdx);
1810 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1811 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1812 Binary |= 1 << ARMII::U_BitShift;
1813 Binary |= ImmOffs;
1814 emitWordLE(Binary);
1815 return;
1816 }
1817 }
1818
1819 // If immediate offset is omitted, default to +0.
1820 Binary |= 1 << ARMII::U_BitShift;
1821
1822 emitWordLE(Binary);
1823 }
1824
1825 void
emitVFPLoadStoreMultipleInstruction(const MachineInstr & MI)1826 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1827 const MCInstrDesc &MCID = MI.getDesc();
1828 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1829
1830 // Part of binary is determined by TableGn.
1831 unsigned Binary = getBinaryCodeForInstr(MI);
1832
1833 // Set the conditional execution predicate
1834 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1835
1836 // Skip operand 0 of an instruction with base register update.
1837 unsigned OpIdx = 0;
1838 if (IsUpdating)
1839 ++OpIdx;
1840
1841 // Set base address operand
1842 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1843
1844 // Set addressing mode by modifying bits U(23) and P(24)
1845 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1846 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1847
1848 // Set bit W(21)
1849 if (IsUpdating)
1850 Binary |= 0x1 << ARMII::W_BitShift;
1851
1852 // First register is encoded in Dd.
1853 Binary |= encodeVFPRd(MI, OpIdx+2);
1854
1855 // Count the number of registers.
1856 unsigned NumRegs = 1;
1857 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1858 const MachineOperand &MO = MI.getOperand(i);
1859 if (!MO.isReg() || MO.isImplicit())
1860 break;
1861 ++NumRegs;
1862 }
1863 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1864 // Otherwise, it will be 0, in the case of 32-bit registers.
1865 if(Binary & 0x100)
1866 Binary |= NumRegs * 2;
1867 else
1868 Binary |= NumRegs;
1869
1870 emitWordLE(Binary);
1871 }
1872
emitMiscInstruction(const MachineInstr & MI)1873 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1874 unsigned Opcode = MI.getDesc().Opcode;
1875 // Part of binary is determined by TableGn.
1876 unsigned Binary = getBinaryCodeForInstr(MI);
1877
1878 if (Opcode == ARM::FCONSTS) {
1879 unsigned Imm = getMachineOpValue(MI, 1);
1880 Binary &= ~(0x780000 >> 19);
1881 Binary |= (Imm & 0x780000) >> 19;
1882 Binary &= ~(0x3800000 >> 7);
1883 Binary |= (Imm & 0x3800000) >> 7;
1884 Binary = VFPThumb2PostEncoder(MI, Binary);
1885 }
1886
1887 // Set the conditional execution predicate
1888 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1889
1890 emitWordLE(Binary);
1891 }
1892
encodeNEONRd(const MachineInstr & MI,unsigned OpIdx)1893 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1894 unsigned RegD = MI.getOperand(OpIdx).getReg();
1895 unsigned Binary = 0;
1896 RegD = getARMRegisterNumbering(RegD);
1897 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1898 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1899 return Binary;
1900 }
1901
encodeNEONRn(const MachineInstr & MI,unsigned OpIdx)1902 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1903 unsigned RegN = MI.getOperand(OpIdx).getReg();
1904 unsigned Binary = 0;
1905 RegN = getARMRegisterNumbering(RegN);
1906 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1907 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1908 return Binary;
1909 }
1910
encodeNEONRm(const MachineInstr & MI,unsigned OpIdx)1911 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1912 unsigned RegM = MI.getOperand(OpIdx).getReg();
1913 unsigned Binary = 0;
1914 RegM = getARMRegisterNumbering(RegM);
1915 Binary |= (RegM & 0xf);
1916 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1917 return Binary;
1918 }
1919
1920 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1921 /// data-processing instruction to the corresponding Thumb encoding.
convertNEONDataProcToThumb(unsigned Binary)1922 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1923 assert((Binary & 0xfe000000) == 0xf2000000 &&
1924 "not an ARM NEON data-processing instruction");
1925 unsigned UBit = (Binary >> 24) & 1;
1926 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1927 }
1928
emitNEONLaneInstruction(const MachineInstr & MI)1929 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1930 unsigned Binary = getBinaryCodeForInstr(MI);
1931
1932 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1933 const MCInstrDesc &MCID = MI.getDesc();
1934 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1935 RegTOpIdx = 0;
1936 RegNOpIdx = 1;
1937 LnOpIdx = 2;
1938 } else { // ARMII::NSetLnFrm
1939 RegTOpIdx = 2;
1940 RegNOpIdx = 0;
1941 LnOpIdx = 3;
1942 }
1943
1944 // Set the conditional execution predicate
1945 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1946
1947 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1948 RegT = getARMRegisterNumbering(RegT);
1949 Binary |= (RegT << ARMII::RegRdShift);
1950 Binary |= encodeNEONRn(MI, RegNOpIdx);
1951
1952 unsigned LaneShift;
1953 if ((Binary & (1 << 22)) != 0)
1954 LaneShift = 0; // 8-bit elements
1955 else if ((Binary & (1 << 5)) != 0)
1956 LaneShift = 1; // 16-bit elements
1957 else
1958 LaneShift = 2; // 32-bit elements
1959
1960 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1961 unsigned Opc1 = Lane >> 2;
1962 unsigned Opc2 = Lane & 3;
1963 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1964 Binary |= (Opc1 << 21);
1965 Binary |= (Opc2 << 5);
1966
1967 emitWordLE(Binary);
1968 }
1969
emitNEONDupInstruction(const MachineInstr & MI)1970 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1971 unsigned Binary = getBinaryCodeForInstr(MI);
1972
1973 // Set the conditional execution predicate
1974 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1975
1976 unsigned RegT = MI.getOperand(1).getReg();
1977 RegT = getARMRegisterNumbering(RegT);
1978 Binary |= (RegT << ARMII::RegRdShift);
1979 Binary |= encodeNEONRn(MI, 0);
1980 emitWordLE(Binary);
1981 }
1982
emitNEON1RegModImmInstruction(const MachineInstr & MI)1983 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1984 unsigned Binary = getBinaryCodeForInstr(MI);
1985 // Destination register is encoded in Dd.
1986 Binary |= encodeNEONRd(MI, 0);
1987 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1988 unsigned Imm = MI.getOperand(1).getImm();
1989 unsigned Op = (Imm >> 12) & 1;
1990 unsigned Cmode = (Imm >> 8) & 0xf;
1991 unsigned I = (Imm >> 7) & 1;
1992 unsigned Imm3 = (Imm >> 4) & 0x7;
1993 unsigned Imm4 = Imm & 0xf;
1994 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1995 if (IsThumb)
1996 Binary = convertNEONDataProcToThumb(Binary);
1997 emitWordLE(Binary);
1998 }
1999
emitNEON2RegInstruction(const MachineInstr & MI)2000 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
2001 const MCInstrDesc &MCID = MI.getDesc();
2002 unsigned Binary = getBinaryCodeForInstr(MI);
2003 // Destination register is encoded in Dd; source register in Dm.
2004 unsigned OpIdx = 0;
2005 Binary |= encodeNEONRd(MI, OpIdx++);
2006 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
2007 ++OpIdx;
2008 Binary |= encodeNEONRm(MI, OpIdx);
2009 if (IsThumb)
2010 Binary = convertNEONDataProcToThumb(Binary);
2011 // FIXME: This does not handle VDUPfdf or VDUPfqf.
2012 emitWordLE(Binary);
2013 }
2014
emitNEON3RegInstruction(const MachineInstr & MI)2015 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
2016 const MCInstrDesc &MCID = MI.getDesc();
2017 unsigned Binary = getBinaryCodeForInstr(MI);
2018 // Destination register is encoded in Dd; source registers in Dn and Dm.
2019 unsigned OpIdx = 0;
2020 Binary |= encodeNEONRd(MI, OpIdx++);
2021 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
2022 ++OpIdx;
2023 Binary |= encodeNEONRn(MI, OpIdx++);
2024 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
2025 ++OpIdx;
2026 Binary |= encodeNEONRm(MI, OpIdx);
2027 if (IsThumb)
2028 Binary = convertNEONDataProcToThumb(Binary);
2029 // FIXME: This does not handle VMOVDneon or VMOVQ.
2030 emitWordLE(Binary);
2031 }
2032
2033 #include "ARMGenCodeEmitter.inc"
2034