1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides ARM specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "ARMMCTargetDesc.h"
15 #include "ARMMCAsmInfo.h"
16 #include "ARMBaseInfo.h"
17 #include "InstPrinter/ARMInstPrinter.h"
18 #include "llvm/MC/MCCodeGenInfo.h"
19 #include "llvm/MC/MCInstrAnalysis.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
26
27 #define GET_REGINFO_MC_DESC
28 #include "ARMGenRegisterInfo.inc"
29
30 #define GET_INSTRINFO_MC_DESC
31 #include "ARMGenInstrInfo.inc"
32
33 #define GET_SUBTARGETINFO_MC_DESC
34 #include "ARMGenSubtargetInfo.inc"
35
36 using namespace llvm;
37
ParseARMTriple(StringRef TT)38 std::string ARM_MC::ParseARMTriple(StringRef TT) {
39 // Set the boolean corresponding to the current target triple, or the default
40 // if one cannot be determined, to true.
41 unsigned Len = TT.size();
42 unsigned Idx = 0;
43
44 // FIXME: Enhance Triple helper class to extract ARM version.
45 bool isThumb = false;
46 if (Len >= 5 && TT.substr(0, 4) == "armv")
47 Idx = 4;
48 else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
49 isThumb = true;
50 if (Len >= 7 && TT[5] == 'v')
51 Idx = 6;
52 }
53
54 std::string ARMArchFeature;
55 if (Idx) {
56 unsigned SubVer = TT[Idx];
57 if (SubVer >= '7' && SubVer <= '9') {
58 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
59 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
60 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
61 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
62 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
63 // FeatureT2XtPk, FeatureMClass
64 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
65 } else
66 // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
67 ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
68 } else if (SubVer == '6') {
69 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
70 ARMArchFeature = "+v6t2";
71 else if (Len >= Idx+2 && TT[Idx+1] == 'm')
72 // v6m: FeatureNoARM, FeatureMClass
73 ARMArchFeature = "+v6t2,+noarm,+mclass";
74 else
75 ARMArchFeature = "+v6";
76 } else if (SubVer == '5') {
77 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
78 ARMArchFeature = "+v5te";
79 else
80 ARMArchFeature = "+v5t";
81 } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
82 ARMArchFeature = "+v4t";
83 }
84
85 if (isThumb) {
86 if (ARMArchFeature.empty())
87 ARMArchFeature = "+thumb-mode";
88 else
89 ARMArchFeature += ",+thumb-mode";
90 }
91
92 return ARMArchFeature;
93 }
94
createARMMCSubtargetInfo(StringRef TT,StringRef CPU,StringRef FS)95 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
96 StringRef FS) {
97 std::string ArchFS = ARM_MC::ParseARMTriple(TT);
98 if (!FS.empty()) {
99 if (!ArchFS.empty())
100 ArchFS = ArchFS + "," + FS.str();
101 else
102 ArchFS = FS;
103 }
104
105 MCSubtargetInfo *X = new MCSubtargetInfo();
106 InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
107 return X;
108 }
109
createARMMCInstrInfo()110 static MCInstrInfo *createARMMCInstrInfo() {
111 MCInstrInfo *X = new MCInstrInfo();
112 InitARMMCInstrInfo(X);
113 return X;
114 }
115
createARMMCRegisterInfo(StringRef Triple)116 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
117 MCRegisterInfo *X = new MCRegisterInfo();
118 InitARMMCRegisterInfo(X, ARM::LR);
119 return X;
120 }
121
createARMMCAsmInfo(const Target & T,StringRef TT)122 static MCAsmInfo *createARMMCAsmInfo(const Target &T, StringRef TT) {
123 Triple TheTriple(TT);
124
125 if (TheTriple.isOSDarwin())
126 return new ARMMCAsmInfoDarwin();
127
128 return new ARMELFMCAsmInfo();
129 }
130
createARMMCCodeGenInfo(StringRef TT,Reloc::Model RM,CodeModel::Model CM,CodeGenOpt::Level OL)131 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
132 CodeModel::Model CM,
133 CodeGenOpt::Level OL) {
134 MCCodeGenInfo *X = new MCCodeGenInfo();
135 if (RM == Reloc::Default) {
136 Triple TheTriple(TT);
137 // Default relocation model on Darwin is PIC, not DynamicNoPIC.
138 RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
139 }
140 X->InitMCCodeGenInfo(RM, CM, OL);
141 return X;
142 }
143
144 // This is duplicated code. Refactor this.
createMCStreamer(const Target & T,StringRef TT,MCContext & Ctx,MCAsmBackend & MAB,raw_ostream & OS,MCCodeEmitter * Emitter,bool RelaxAll,bool NoExecStack)145 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
146 MCContext &Ctx, MCAsmBackend &MAB,
147 raw_ostream &OS,
148 MCCodeEmitter *Emitter,
149 bool RelaxAll,
150 bool NoExecStack) {
151 Triple TheTriple(TT);
152
153 if (TheTriple.isOSDarwin())
154 return createMachOStreamer(Ctx, MAB, OS, Emitter, false);
155
156 if (TheTriple.isOSWindows()) {
157 llvm_unreachable("ARM does not support Windows COFF format");
158 }
159
160 return createELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack);
161 }
162
createARMMCInstPrinter(const Target & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI,const MCSubtargetInfo & STI)163 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
164 unsigned SyntaxVariant,
165 const MCAsmInfo &MAI,
166 const MCInstrInfo &MII,
167 const MCRegisterInfo &MRI,
168 const MCSubtargetInfo &STI) {
169 if (SyntaxVariant == 0)
170 return new ARMInstPrinter(MAI, MII, MRI, STI);
171 return 0;
172 }
173
174 namespace {
175
176 class ARMMCInstrAnalysis : public MCInstrAnalysis {
177 public:
ARMMCInstrAnalysis(const MCInstrInfo * Info)178 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
179
isUnconditionalBranch(const MCInst & Inst) const180 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
181 // BCCs with the "always" predicate are unconditional branches.
182 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
183 return true;
184 return MCInstrAnalysis::isUnconditionalBranch(Inst);
185 }
186
isConditionalBranch(const MCInst & Inst) const187 virtual bool isConditionalBranch(const MCInst &Inst) const {
188 // BCCs with the "always" predicate are unconditional branches.
189 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
190 return false;
191 return MCInstrAnalysis::isConditionalBranch(Inst);
192 }
193
evaluateBranch(const MCInst & Inst,uint64_t Addr,uint64_t Size) const194 uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr,
195 uint64_t Size) const {
196 // We only handle PCRel branches for now.
197 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
198 return -1ULL;
199
200 int64_t Imm = Inst.getOperand(0).getImm();
201 // FIXME: This is not right for thumb.
202 return Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
203 }
204 };
205
206 }
207
createARMMCInstrAnalysis(const MCInstrInfo * Info)208 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
209 return new ARMMCInstrAnalysis(Info);
210 }
211
212 // Force static initialization.
LLVMInitializeARMTargetMC()213 extern "C" void LLVMInitializeARMTargetMC() {
214 // Register the MC asm info.
215 RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
216 RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
217
218 // Register the MC codegen info.
219 TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
220 TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
221
222 // Register the MC instruction info.
223 TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
224 TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
225
226 // Register the MC register info.
227 TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
228 TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
229
230 // Register the MC subtarget info.
231 TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
232 ARM_MC::createARMMCSubtargetInfo);
233 TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
234 ARM_MC::createARMMCSubtargetInfo);
235
236 // Register the MC instruction analyzer.
237 TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
238 createARMMCInstrAnalysis);
239 TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
240 createARMMCInstrAnalysis);
241
242 // Register the MC Code Emitter
243 TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
244 TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
245
246 // Register the asm backend.
247 TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
248 TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
249
250 // Register the object streamer.
251 TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
252 TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
253
254 // Register the MCInstPrinter.
255 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
256 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
257 }
258