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1 //===-- SPUTargetMachine.cpp - Define TargetMachine for Cell SPU ----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the Cell SPU target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SPUTargetMachine.h"
15 #include "SPU.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/CodeGen/SchedulerRegistry.h"
18 #include "llvm/Support/DynamicLibrary.h"
19 #include "llvm/Support/TargetRegistry.h"
20 
21 using namespace llvm;
22 
LLVMInitializeCellSPUTarget()23 extern "C" void LLVMInitializeCellSPUTarget() {
24   // Register the target.
25   RegisterTargetMachine<SPUTargetMachine> X(TheCellSPUTarget);
26 }
27 
28 const std::pair<unsigned, int> *
getCalleeSaveSpillSlots(unsigned & NumEntries) const29 SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const {
30   NumEntries = 1;
31   return &LR[0];
32 }
33 
SPUTargetMachine(const Target & T,StringRef TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Reloc::Model RM,CodeModel::Model CM,CodeGenOpt::Level OL)34 SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT,
35                                    StringRef CPU, StringRef FS,
36                                    const TargetOptions &Options,
37                                    Reloc::Model RM, CodeModel::Model CM,
38                                    CodeGenOpt::Level OL)
39   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
40     Subtarget(TT, CPU, FS),
41     DataLayout(Subtarget.getTargetDataString()),
42     InstrInfo(*this),
43     FrameLowering(Subtarget),
44     TLInfo(*this),
45     TSInfo(*this),
46     InstrItins(Subtarget.getInstrItineraryData()) {
47 }
48 
49 //===----------------------------------------------------------------------===//
50 // Pass Pipeline Configuration
51 //===----------------------------------------------------------------------===//
52 
53 namespace {
54 /// SPU Code Generator Pass Configuration Options.
55 class SPUPassConfig : public TargetPassConfig {
56 public:
SPUPassConfig(SPUTargetMachine * TM,PassManagerBase & PM)57   SPUPassConfig(SPUTargetMachine *TM, PassManagerBase &PM)
58     : TargetPassConfig(TM, PM) {}
59 
getSPUTargetMachine() const60   SPUTargetMachine &getSPUTargetMachine() const {
61     return getTM<SPUTargetMachine>();
62   }
63 
64   virtual bool addInstSelector();
65   virtual bool addPreEmitPass();
66 };
67 } // namespace
68 
createPassConfig(PassManagerBase & PM)69 TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM) {
70   return new SPUPassConfig(this, PM);
71 }
72 
addInstSelector()73 bool SPUPassConfig::addInstSelector() {
74   // Install an instruction selector.
75   PM.add(createSPUISelDag(getSPUTargetMachine()));
76   return false;
77 }
78 
79 // passes to run just before printing the assembly
addPreEmitPass()80 bool SPUPassConfig::addPreEmitPass() {
81   // load the TCE instruction scheduler, if available via
82   // loaded plugins
83   typedef llvm::FunctionPass* (*BuilderFunc)(const char*);
84   BuilderFunc schedulerCreator =
85     (BuilderFunc)(intptr_t)sys::DynamicLibrary::SearchForAddressOfSymbol(
86           "createTCESchedulerPass");
87   if (schedulerCreator != NULL)
88       PM.add(schedulerCreator("cellspu"));
89 
90   //align instructions with nops/lnops for dual issue
91   PM.add(createSPUNopFillerPass(getSPUTargetMachine()));
92   return true;
93 }
94