1 /* 2 * Copyright (c) 2008, Google Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in 12 * the documentation and/or other materials provided with the 13 * distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 18 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 19 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 25 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef __ASM_ARCH_MSM7200_VIC_H 30 #define __ASM_ARCH_MSM7200_VIC_H 31 32 #define MSM_VIC_BASE 0xC0000000 33 34 #define VIC_REG(off) (MSM_VIC_BASE + (off)) 35 36 /* See 80-VE113-1 A, pp 218-228 */ 37 38 #define VIC_IRQ_STATUS0 VIC_REG(0x0000) 39 #define VIC_IRQ_STATUS1 VIC_REG(0x0004) 40 #define VIC_FIQ_STATUS0 VIC_REG(0x0008) 41 #define VIC_FIQ_STATUS1 VIC_REG(0x000C) 42 #define VIC_RAW_STATUS0 VIC_REG(0x0010) 43 #define VIC_RAW_STATUS1 VIC_REG(0x0014) 44 #define VIC_INT_CLEAR0 VIC_REG(0x0018) 45 #define VIC_INT_CLEAR1 VIC_REG(0x001C) 46 #define VIC_INT_SELECT0 VIC_REG(0x0020) /* 1: FIQ, 0: IRQ */ 47 #define VIC_INT_SELECT1 VIC_REG(0x0024) /* 1: FIQ, 0: IRQ */ 48 #define VIC_INT_EN0 VIC_REG(0x0028) 49 #define VIC_INT_EN1 VIC_REG(0x002C) 50 #define VIC_INT_ENCLEAR0 VIC_REG(0x0040) 51 #define VIC_INT_ENCLEAR1 VIC_REG(0x0044) 52 #define VIC_SOFTINT0 VIC_REG(0x0050) 53 #define VIC_SOFTINT1 VIC_REG(0x0054) 54 #define VIC_INT_MASTEREN VIC_REG(0x0060) /* 1: IRQ, 2: FIQ */ 55 #define VIC_PROTECTION VIC_REG(0x0064) /* 1: ENABLE */ 56 #define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */ 57 #define VIC_INT_TYPE0 VIC_REG(0x0070) /* 1: EDGE, 0: LEVEL */ 58 #define VIC_INT_TYPE1 VIC_REG(0x0074) /* 1: EDGE, 0: LEVEL */ 59 #define VIC_IRQ_VEC_RD VIC_REG(0x0F00) /* pending int # */ 60 #define VIC_IRQ_VEC_PEND_RD VIC_REG(0x0F20) /* pending vector addr */ 61 62 #define VIC_VECTADDR(n) VIC_REG(0x0100+((n) * 4)) 63 #define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4)) 64 65 #endif 66