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Searched refs:Amt (Results 1 – 25 of 32) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Drotate.ll4 define i32 @rotl32(i32 %A, i8 %Amt) {
5 %shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
7 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
14 define i32 @rotr32(i32 %A, i8 %Amt) {
15 %shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
17 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
38 define i16 @rotl16(i16 %A, i8 %Amt) {
39 %shift.upgrd.5 = zext i8 %Amt to i16 ; <i16> [#uses=1]
41 %Amt2 = sub i8 16, %Amt ; <i8> [#uses=1]
48 define i16 @rotr16(i16 %A, i8 %Amt) {
[all …]
/external/llvm/test/CodeGen/PowerPC/
Drotl-2.ll5 define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
6 %shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
8 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
15 define i32 @rotr32(i32 %A, i8 %Amt) nounwind {
16 %shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
18 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
Drotl-64.ll12 define i64 @t2(i64 %A, i8 zeroext %Amt) {
13 %Amt1 = zext i8 %Amt to i64
15 %Amt2 = sub i8 64, %Amt
/external/llvm/test/CodeGen/CellSPU/
Drotate_ops.ll64 define i32 @rotr32_1(i32 %A, i8 %Amt) {
65 %tmp1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
67 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
74 define i32 @rotr32_2(i32 %A, i8 %Amt) {
75 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
76 %tmp1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
133 define i8 @rotl8(i8 %A, i8 %Amt) {
134 %B = shl i8 %A, %Amt ; <i8> [#uses=1]
135 %Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
141 define i8 @rotr8(i8 %A, i8 %Amt) {
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/external/clang/lib/Analysis/
DFormatString.cpp81 const OptionalAmount &Amt = ParseAmount(I, E); in ParsePositionAmount() local
83 if (Amt.getHowSpecified() == OptionalAmount::NotSpecified) { in ParsePositionAmount()
94 assert(Amt.getHowSpecified() == OptionalAmount::Constant); in ParsePositionAmount()
100 if (Amt.getConstantAmount() == 0) { in ParsePositionAmount()
108 return OptionalAmount(OptionalAmount::Arg, Amt.getConstantAmount() - 1, in ParsePositionAmount()
131 const OptionalAmount Amt = in ParseFieldWidth() local
135 if (Amt.isInvalid()) in ParseFieldWidth()
137 CS.setFieldWidth(Amt); in ParseFieldWidth()
150 const OptionalAmount &Amt = ParseAmount(I, E); in ParseArgPosition() local
158 if (Amt.getHowSpecified() == OptionalAmount::Constant && *(I++) == '$') { in ParseArgPosition()
[all …]
DScanfFormatString.cpp123 const OptionalAmount &Amt = clang::analyze_format_string::ParseAmount(I, E); in ParseScanfSpecifier() local
124 if (Amt.getHowSpecified() != OptionalAmount::NotSpecified) { in ParseScanfSpecifier()
125 assert(Amt.getHowSpecified() == OptionalAmount::Constant); in ParseScanfSpecifier()
126 FS.setFieldWidth(Amt); in ParseScanfSpecifier()
DPrintfFormatString.cpp42 const OptionalAmount Amt = ParsePositionAmount(H, Start, Beg, E, in ParsePrecision() local
44 if (Amt.isInvalid()) in ParsePrecision()
46 FS.setPrecision(Amt); in ParsePrecision()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h86 static inline unsigned rotr32(unsigned Val, unsigned Amt) { in rotr32() argument
87 assert(Amt < 32 && "Invalid rotate amount"); in rotr32()
88 return (Val >> Amt) | (Val << ((32-Amt)&31)); in rotr32()
93 static inline unsigned rotl32(unsigned Val, unsigned Amt) { in rotl32() argument
94 assert(Amt < 32 && "Invalid rotate amount"); in rotl32()
95 return (Val << Amt) | (Val >> ((32-Amt)&31)); in rotl32()
/external/llvm/include/llvm/ADT/
DAPSInt.h114 APSInt operator>>(unsigned Amt) const {
115 return IsUnsigned ? APSInt(lshr(Amt), true) : APSInt(ashr(Amt), false);
117 APSInt& operator>>=(unsigned Amt) {
118 *this = *this >> Amt;
145 APSInt& operator<<=(unsigned Amt) {
146 *this = *this << Amt;
DAPInt.h841 APInt sshl_ov(unsigned Amt, bool &Overflow) const;
/external/clang/lib/StaticAnalyzer/Core/
DBasicValueFactory.cpp181 uint64_t Amt = V2.getZExtValue(); in evalAPSInt() local
183 if (Amt > V1.getBitWidth()) in evalAPSInt()
186 return &getValue( V1.operator<<( (unsigned) Amt )); in evalAPSInt()
199 uint64_t Amt = V2.getZExtValue(); in evalAPSInt() local
201 if (Amt > V1.getBitWidth()) in evalAPSInt()
204 return &getValue( V1.operator>>( (unsigned) Amt )); in evalAPSInt()
/external/llvm/test/CodeGen/Generic/
Dshift-int64.ll8 define i64 @test_variable(i64 %X, i8 %Amt) {
9 %shift.upgrd.1 = zext i8 %Amt to i64 ; <i64> [#uses=1]
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp1261 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, in ExpandShiftByConstant() argument
1274 if (Amt > VTBits) { in ExpandShiftByConstant()
1276 } else if (Amt > NVTBits) { in ExpandShiftByConstant()
1279 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy)); in ExpandShiftByConstant()
1280 } else if (Amt == NVTBits) { in ExpandShiftByConstant()
1283 } else if (Amt == 1 && in ExpandShiftByConstant()
1293 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy)); in ExpandShiftByConstant()
1296 DAG.getConstant(Amt, ShTy)), in ExpandShiftByConstant()
1298 DAG.getConstant(NVTBits-Amt, ShTy))); in ExpandShiftByConstant()
1304 if (Amt > VTBits) { in ExpandShiftByConstant()
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DLegalizeTypes.h340 void ExpandShiftByConstant(SDNode *N, unsigned Amt,
/external/llvm/test/Transforms/InstCombine/
Drem.ll35 %Amt = shl i32 32, %shift.upgrd.1
36 %V = urem i32 %X, %Amt
/external/llvm/include/llvm/
DBasicBlock.h277 void AdjustBlockAddressRefCount(int Amt) {
278 setValueSubclassData(getSubclassDataFromValue()+Amt);
/external/clang/include/clang/Analysis/Analyses/
DFormatString.h344 void setFieldWidth(const OptionalAmount &Amt) { in setFieldWidth() argument
345 FieldWidth = Amt; in setFieldWidth()
447 void setPrecision(const OptionalAmount &Amt) { in setPrecision() argument
448 Precision = Amt; in setPrecision()
/external/llvm/lib/Transforms/InstCombine/
DInstCombineCasts.cpp120 Value *Amt = 0; in PromoteCastOfAllocation() local
122 Amt = NumElements; in PromoteCastOfAllocation()
124 Amt = ConstantInt::get(AI.getArraySize()->getType(), Scale); in PromoteCastOfAllocation()
126 Amt = AllocaBuilder.CreateMul(Amt, NumElements); in PromoteCastOfAllocation()
132 Amt = AllocaBuilder.CreateAdd(Amt, Off); in PromoteCastOfAllocation()
135 AllocaInst *New = AllocaBuilder.CreateAlloca(CastElTy, Amt); in PromoteCastOfAllocation()
700 if (ConstantInt *Amt = dyn_cast<ConstantInt>(I->getOperand(1))) { in CanEvaluateZExtd() local
703 BitsToClear += Amt->getZExtValue(); in CanEvaluateZExtd()
/external/clang/lib/Sema/
DSemaChecking.cpp2110 bool HandleAmount(const analyze_format_string::OptionalAmount &Amt, unsigned k,
2113 const analyze_printf::OptionalAmount &Amt,
2140 const analyze_format_string::OptionalAmount &Amt, in HandleAmount() argument
2144 if (Amt.hasDataArgument()) { in HandleAmount()
2146 unsigned argIndex = Amt.getArgIndex(); in HandleAmount()
2150 getLocationOfByte(Amt.getStart()), in HandleAmount()
2166 const analyze_printf::ArgTypeResult &ATR = Amt.getArgType(S.Context); in HandleAmount()
2173 getLocationOfByte(Amt.getStart()), in HandleAmount()
2187 const analyze_printf::OptionalAmount &Amt, in HandleInvalidAmount() argument
2195 Amt.getHowSpecified() == analyze_printf::OptionalAmount::Constant in HandleInvalidAmount()
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/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp576 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand() local
578 O << ", asr #" << (Amt == 0 ? 32 : Amt); in printShiftImmOperand()
579 else if (Amt) in printShiftImmOperand()
580 O << ", lsl #" << Amt; in printShiftImmOperand()
/external/llvm/lib/Support/Unix/
DPath.inc784 while (ssize_t Amt = ::read(inFile, Buffer, 16*1024)) {
785 if (Amt == -1) {
793 while (Amt) {
794 ssize_t AmtWritten = ::write(outFile, BufPtr, Amt);
803 Amt -= AmtWritten;
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp3855 SDValue Amt = Op.getOperand(2); in LowerSHL_PARTS() local
3856 EVT AmtVT = Amt.getValueType(); in LowerSHL_PARTS()
3859 DAG.getConstant(BitWidth, AmtVT), Amt); in LowerSHL_PARTS()
3860 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); in LowerSHL_PARTS()
3863 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, in LowerSHL_PARTS()
3867 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); in LowerSHL_PARTS()
3884 SDValue Amt = Op.getOperand(2); in LowerSRL_PARTS() local
3885 EVT AmtVT = Amt.getValueType(); in LowerSRL_PARTS()
3888 DAG.getConstant(BitWidth, AmtVT), Amt); in LowerSRL_PARTS()
3889 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); in LowerSRL_PARTS()
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/external/llvm/lib/VMCore/
DConstantFold.cpp249 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1)); in ExtractConstantBytes() local
250 if (Amt == 0) in ExtractConstantBytes()
252 unsigned ShAmt = Amt->getZExtValue(); in ExtractConstantBytes()
271 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1)); in ExtractConstantBytes() local
272 if (Amt == 0) in ExtractConstantBytes()
274 unsigned ShAmt = Amt->getZExtValue(); in ExtractConstantBytes()
DInstructions.cpp794 static Value *getAISize(LLVMContext &Context, Value *Amt) { in getAISize() argument
795 if (!Amt) in getAISize()
796 Amt = ConstantInt::get(Type::getInt32Ty(Context), 1); in getAISize()
798 assert(!isa<BasicBlock>(Amt) && in getAISize()
800 assert(Amt->getType()->isIntegerTy() && in getAISize()
803 return Amt; in getAISize()
/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.cpp162 unsigned Amt = ARM_AM::getAM2Offset(OffImm); in convertToThreeAddress() local
164 if (ARM_AM::getSOImmVal(Amt) == -1) in convertToThreeAddress()
170 .addReg(BaseReg).addImm(Amt) in convertToThreeAddress()
172 } else if (Amt != 0) { in convertToThreeAddress()
174 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); in convertToThreeAddress()
188 unsigned Amt = ARM_AM::getAM3Offset(OffImm); in convertToThreeAddress() local
193 .addReg(BaseReg).addImm(Amt) in convertToThreeAddress()

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