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Searched refs:CP0_Config3 (Results 1 – 5 of 5) sorted by relevance

/external/qemu/target-mips/
Dtranslate_init.c70 int32_t CP0_Config3; member
109 .CP0_Config3 = MIPS_CONFIG3,
130 .CP0_Config3 = MIPS_CONFIG3,
149 .CP0_Config3 = MIPS_CONFIG3,
168 .CP0_Config3 = MIPS_CONFIG3,
188 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
208 .CP0_Config3 = MIPS_CONFIG3,
228 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
249 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
272 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT),
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Dmachine.c127 qemu_put_sbe32s(f, &env->CP0_Config3); in cpu_save()
279 qemu_get_sbe32s(f, &env->CP0_Config3); in cpu_load()
Dcpu.h362 int32_t CP0_Config3; member
Dtranslate.c3236 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3)); in gen_mfc0()
4403 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3)); in gen_dmfc0()
8621 env->CP0_Config3 = env->cpu_model->CP0_Config3; in cpu_reset()
Dop_helper.c1125 if (env->CP0_Config3 & (1 << CP0C3_MT)) { in helper_mtc0_entryhi()