Searched refs:CP0_Status (Results 1 – 8 of 8) sorted by relevance
59 if (!(env->CP0_Status & (1 << CP0St_EXL)) && in compute_hflags()60 !(env->CP0_Status & (1 << CP0St_ERL)) && in compute_hflags()62 env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; in compute_hflags()66 (env->CP0_Status & (1 << CP0St_PX)) || in compute_hflags()67 (env->CP0_Status & (1 << CP0St_UX))) in compute_hflags()69 if (env->CP0_Status & (1 << CP0St_UX)) in compute_hflags()72 if ((env->CP0_Status & (1 << CP0St_CU0)) || in compute_hflags()75 if (env->CP0_Status & (1 << CP0St_CU1)) in compute_hflags()77 if (env->CP0_Status & (1 << CP0St_FR)) in compute_hflags()90 if (env->CP0_Status & (1 << CP0St_CU3)) in compute_hflags()
51 if (!(env->CP0_Status & (1 << CP0St_ERL))) in fixed_mmu_map_address()111 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; in get_physical_address()112 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; in get_physical_address()113 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; in get_physical_address()123 if (env->CP0_Status & (1 << CP0St_ERL)) { in get_physical_address()428 if (!(env->CP0_Status & (1 << CP0St_EXL))) in do_interrupt()436 env->CP0_Status |= (1 << CP0St_SR); in do_interrupt()440 env->CP0_Status |= (1 << CP0St_NMI); in do_interrupt()450 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); in do_interrupt()453 if (!(env->CP0_Status & (1 << CP0St_EXL))) in do_interrupt()[all …]
46 if (!(env->CP0_Status & (1 << CP0St_EXL)) && in helper_interrupt_restart()47 !(env->CP0_Status & (1 << CP0St_ERL)) && in helper_interrupt_restart()49 (env->CP0_Status & (1 << CP0St_IE)) && in helper_interrupt_restart()50 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) { in helper_interrupt_restart()724 t0 = env->CP0_Status & ~0xf1000018; in helper_mftc0_status()1160 old = env->CP0_Status; in helper_mtc0_status()1161 env->CP0_Status = (env->CP0_Status & ~mask) | val; in helper_mtc0_status()1183 env->CP0_Status = arg1 & ~0xf1000018; in helper_mttc0_status()1652 target_ulong t0 = env->CP0_Status; in helper_di()1654 env->CP0_Status = t0 & ~(1 << CP0St_IE); in helper_di()[all …]
268 int32_t CP0_Status; member508 return ((env->CP0_Status & in is_cpu_user()
116 qemu_put_sbe32s(f, &env->CP0_Status); in cpu_save()268 qemu_get_sbe32s(f, &env->CP0_Status); in cpu_load()
3163 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status)); in gen_mfc0()4331 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status)); in gen_dmfc0()8516 env->CP0_Status, env->CP0_Cause, env->CP0_EPC); in cpu_dump_state()8682 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); in cpu_reset()
9 if ((env->CP0_Status & (1 << CP0St_IE)) && in cpu_mips_update_irq()10 !(env->CP0_Status & (1 << CP0St_EXL)) && in cpu_mips_update_irq()11 !(env->CP0_Status & (1 << CP0St_ERL)) && in cpu_mips_update_irq()13 if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) && in cpu_mips_update_irq()
987 if (env->CP0_Status & (1 << CP0St_FR)) in cpu_gdb_read_register()998 case 32: GET_REGL((int32_t)env->CP0_Status); in cpu_gdb_read_register()1039 if (env->CP0_Status & (1 << CP0St_FR)) in cpu_gdb_write_register()1059 case 32: env->CP0_Status = tmp; break; in cpu_gdb_write_register()