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Searched refs:CPSR_I (Results 1 – 4 of 4) sorted by relevance

/external/qemu/target-arm/
Dhelper.c289 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; in cpu_reset()
295 env->uncached_cpsr &= ~CPSR_I; in cpu_reset()
846 mask = CPSR_I; in do_interrupt()
871 mask = CPSR_I; in do_interrupt()
890 mask = CPSR_A | CPSR_I; in do_interrupt()
896 mask = CPSR_A | CPSR_I; in do_interrupt()
903 mask = CPSR_A | CPSR_I; in do_interrupt()
910 mask = CPSR_A | CPSR_I | CPSR_F; in do_interrupt()
924 mask = CPSR_A | CPSR_I | CPSR_F; in do_interrupt()
2239 return (env->uncached_cpsr & CPSR_I) != 0; in HELPER()
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Dcpu.h266 #define CPSR_I (1 << 7) macro
Dtranslate.c6639 mask |= CPSR_I; in disas_arm_insn()
8457 offset |= CPSR_I; in disas_thumb2_insn()
8461 imm = CPSR_A | CPSR_I | CPSR_F; in disas_thumb2_insn()
9438 shift = CPSR_A | CPSR_I | CPSR_F; in disas_thumb_insn()
/external/qemu/
Dcpu-exec.c540 || !(env->uncached_cpsr & CPSR_I))) { in cpu_exec()