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Searched refs:CPU_TLB_SIZE (Results 1 – 12 of 12) sorted by relevance

/external/qemu/
Dcpu-defs.h77 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) macro
109 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
110 target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
Dsoftmmu_template.h113 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); in glue()
170 if ((invalidate_cache == 2) && (index < CPU_TLB_SIZE)) { in glue()
201 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); in glue()
288 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); in glue()
346 if ((invalidate_cache == 2) && (index < CPU_TLB_SIZE)) { in glue()
376 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); in glue()
Dsoftmmu_header.h91 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); in glue()
112 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); in glue()
137 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); in glue()
Dexec-all.h394 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); in get_phys_addr_code()
Dexec.c1799 for(i = 0; i < CPU_TLB_SIZE; i++) { in tlb_flush()
1845 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); in tlb_flush_page()
1910 for(i = 0; i < CPU_TLB_SIZE; i++) in cpu_physical_memory_reset_dirty()
1962 for(i = 0; i < CPU_TLB_SIZE; i++) in cpu_tlb_update_dirty()
1981 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); in tlb_set_dirty()
2057 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); in tlb_set_page_exec()
/external/qemu/memcheck/
Dmemcheck_util.c185 target_ulong index = (start >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); in invalidate_tlb_cache()
186 const target_ulong to = ((end - 1) >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE-1); in invalidate_tlb_cache()
/external/qemu/tcg/x86_64/
Dtcg-target.c593 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS); in tcg_out_qemu_ld()
788 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS); in tcg_out_qemu_st()
/external/qemu/tcg/sparc/
Dtcg-target.c774 tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS); in tcg_out_qemu_ld()
986 tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS); in tcg_out_qemu_st()
/external/qemu/tcg/arm/
Dtcg-target.c996 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1); in tcg_out_qemu_ld()
1216 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1); in tcg_out_qemu_st()
/external/qemu/tcg/hppa/
Dtcg-target.c918 if (check_fit_tl(offset + CPU_TLB_SIZE, 14)) { in tcg_out_tlb_read()
/external/qemu/target-mips/
Dop_helper.c1876 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); in v2p_mmu()
1905 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); in v2p()
/external/qemu/tcg/i386/
Dtcg-target.c1026 (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS, 0); in tcg_out_tlb_load()