| /external/llvm/lib/Target/ARM/ |
| D | Thumb2ITBlockPass.cpp | 45 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
109 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, in MoveCopyOutOfITBlock()
157 ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg); in MoveCopyOutOfITBlock()
174 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in InsertITInstructions()
197 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); in InsertITInstructions()
210 ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg); in InsertITInstructions()
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| D | ARMBaseInstrInfo.h | 77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { in getPredicate()
79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm() in getPredicate()
346 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
362 ARMCC::CondCodes Pred, unsigned PredReg,
368 ARMCC::CondCodes Pred, unsigned PredReg,
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| D | Thumb2InstrInfo.cpp | 61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); in ReplaceTailWithBranchTo()
180 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate()
576 ARMCC::CondCodes CC = getInstrPredicate(UseMI, PredReg); in scheduleTwoAddrSource()
583 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); in scheduleTwoAddrSource()
592 ARMCC::CondCodes NCC = getInstrPredicate(NMI, PredReg); in scheduleTwoAddrSource()
608 ARMCC::CondCodes
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| D | ARMLoadStoreOptimizer.cpp | 95 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
108 ARMCC::CondCodes Pred,
115 ARMCC::CondCodes Pred, unsigned PredReg,
285 int Opcode, ARMCC::CondCodes Pred, in MergeOps()
371 ARMCC::CondCodes Pred, unsigned PredReg, in MergeOpsUpdate()
448 ARMCC::CondCodes Pred, unsigned PredReg, in MergeLDR_STR()
533 ARMCC::CondCodes Pred, unsigned PredReg) { in isMatchingDecrement()
566 ARMCC::CondCodes Pred, unsigned PredReg) { in isMatchingIncrement()
721 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in MergeBaseUpdateLSMultiple()
874 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in MergeBaseUpdateLoadStore()
[all …]
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| D | Thumb2RegisterInfo.h | 36 ARMCC::CondCodes Pred = ARMCC::AL,
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| D | Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool()
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| D | Thumb1RegisterInfo.h | 41 ARMCC::CondCodes Pred = ARMCC::AL,
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| D | Thumb2InstrInfo.h | 75 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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| D | MLxExpansionPass.cpp | 218 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm(); in ExpandFPMLxInstruction()
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| D | ARMBaseRegisterInfo.cpp | 694 ARMCC::CondCodes Pred, in emitLoadConstPool()
729 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitSPUpdate()
765 ARMCC::CondCodes Pred = (PIdx == -1) in eliminateCallFramePseudoInstr()
766 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); in eliminateCallFramePseudoInstr()
1106 ARMCC::CondCodes Pred = (PIdx == -1) in eliminateFrameIndex()
1107 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); in eliminateFrameIndex()
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| D | ARMBaseInstrInfo.cpp | 157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); in convertToThreeAddress()
435 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); in ReverseBranchCondition()
483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); in SubsumesPredicate()
484 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); in SubsumesPredicate()
1479 ARMCC::CondCodes
1488 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); in getInstrPredicate()
1511 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstruction()
1580 ARMCC::CondCodes Pred, unsigned PredReg, in emitARMRegPlusImmediate()
1920 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm(); in OptimizeCompareInstr()
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| D | ARMBaseRegisterInfo.h | 167 ARMCC::CondCodes Pred = ARMCC::AL,
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| D | Thumb2SizeReduction.cpp | 153 bool is2Addr, ARMCC::CondCodes Pred,
253 bool is2Addr, ARMCC::CondCodes Pred, in VerifyPredAndCC()
643 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceTo2Addr()
735 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceToNarrow()
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| D | ARMISelDAGToDAG.cpp | 249 ARMCC::CondCodes CCVal, SDValue CCR,
252 ARMCC::CondCodes CCVal, SDValue CCR,
255 ARMCC::CondCodes CCVal, SDValue CCR,
258 ARMCC::CondCodes CCVal, SDValue CCR,
2174 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { in SelectT2CMOVShiftOp()
2200 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { in SelectARMCMOVShiftOp()
2220 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { in SelectT2CMOVImmOp()
2251 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { in SelectARMCMOVImmOp()
2291 ARMCC::CondCodes CCVal = in SelectCMOVOp()
2292 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue(); in SelectCMOVOp()
[all …]
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| D | ARMConstantIslandPass.cpp | 1372 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in createNewWater()
1604 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm(); in fixupConditionalBr()
1819 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg); in optimizeThumb2Branches()
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| D | ARMISelLowering.h | 525 ARMCC::CondCodes Cond) const;
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| D | Thumb1RegisterInfo.cpp | 69 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 130 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in ReverseBranchCondition()
225 MSP430CC::CondCodes BranchCode = in AnalyzeBranch()
226 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm()); in AnalyzeBranch()
248 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in AnalyzeBranch()
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| D | MSP430.h | 23 enum CondCodes { enum
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| /external/llvm/lib/Target/Sparc/ |
| D | Sparc.h | 37 enum CondCodes { enum
74 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { in SPARCCondCodeToString()
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| D | SparcInstrInfo.cpp | 79 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) in GetOppositeBranchCondition()
181 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm(); in AnalyzeBranch()
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| D | SparcAsmPrinter.cpp | 177 O << SPARCCondCodeToString((SPCC::CondCodes)CC); in printCCOperand()
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| D | SparcISelLowering.cpp | 644 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { in IntCondCCodeToICC()
662 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { in FPCondCCodeToFCC()
1184 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); in EmitInstrWithCustomInserter()
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMBaseInfo.h | 29 enum CondCodes { // Meaning (integer) Meaning (floating-point) enum
47 inline static CondCodes getOppositeCondition(CondCodes CC) { in getOppositeCondition()
68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { in ARMCondCodeToString()
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 693 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printPredicateOperand()
704 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printMandatoryPredicateOperand()
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