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Searched refs:EXTRACT_SUBREG (Results 1 – 16 of 16) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsDerived.td17 … (Hexagon_M2_maci (EXTRACT_SUBREG (MPYU64 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg),
18 … (EXTRACT_SUBREG DoubleRegs:$src2, subreg_loreg)),
20 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg),
21 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg)),
22 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_loreg),
23 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)),
24 (EXTRACT_SUBREG (MPYU64 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg),
25 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_loreg)),
DHexagonSelectCCInfo.td104 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_hireg),
105 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_hireg)),
107 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_loreg),
108 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_loreg)))>;
116 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_hireg),
117 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_hireg)),
120 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_loreg),
121 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_loreg)))>;
DHexagonInstrInfo.td2671 (i64 (SXTW (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg)))>;
2675 (i64 (SXTW (SXTH (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg))))>;
2679 (i64 (SXTW (SXTB (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg))))>;
2719 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg),
2720 (EXTRACT_SUBREG DoubleRegs:$src3, subreg_hireg)),
2722 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_loreg),
2723 (EXTRACT_SUBREG DoubleRegs:$src3, subreg_loreg)))>;
2737 (i32 (EXTRACT_SUBREG DoubleRegs:$src, subreg_loreg))>;
2741 (i1 (TFR_PdRs (i32(EXTRACT_SUBREG DoubleRegs:$src, subreg_loreg))))>;
2745 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
[all …]
/external/llvm/lib/Target/X86/
DX86InstrCompiler.td1124 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1139 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1145 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1266 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1274 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1281 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1284 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1290 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1297 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1300 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
[all …]
DX86InstrSSE.td248 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
250 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
262 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
265 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
267 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
566 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
569 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
[all …]
DX86InstrArithmetic.td1189 // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the
/external/llvm/include/llvm/Target/
DTargetOpcodes.h41 EXTRACT_SUBREG = 6, enumerator
DTarget.td650 def EXTRACT_SUBREG : Instruction {
/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp226 case TargetOpcode::EXTRACT_SUBREG: in runOnMachineFunction()
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td3925 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3931 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3937 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3952 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3959 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3974 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3981 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4025 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4033 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4042 (v2f32 (EXTRACT_SUBREG QPR:$src3,
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp264 case TargetOpcode::EXTRACT_SUBREG: in isResourceAvailable()
304 case TargetOpcode::EXTRACT_SUBREG: in reserveResources()
DScheduleDAGRRList.cpp1860 if (Opc == TargetOpcode::EXTRACT_SUBREG || in getNodePriority()
2078 if (Opc == TargetOpcode::EXTRACT_SUBREG || in unscheduledNode()
2107 if (POpc == TargetOpcode::EXTRACT_SUBREG || in unscheduledNode()
2550 if (Opc == TargetOpcode::EXTRACT_SUBREG || in canEnableCoalescing()
2922 if (SuccOpc == TargetOpcode::EXTRACT_SUBREG || in AddPseudoTwoAddrDeps()
DInstrEmitter.cpp449 if (Opc == TargetOpcode::EXTRACT_SUBREG) { in EmitSubregNode()
669 if (Opc == TargetOpcode::EXTRACT_SUBREG || in EmitMachineNode()
DSelectionDAG.cpp5184 SDNode *Subreg = getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, in getTargetExtractSubreg()
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td294 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
299 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1135 (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
1210 (BIT8rr (EXTRACT_SUBREG GR16:$src, subreg_8bit),
1211 (EXTRACT_SUBREG GR16:$src2, subreg_8bit))>;
/external/llvm/lib/Target/Mips/
DMips64InstrInfo.td277 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>;