Searched refs:IR (Results 1 – 25 of 229) sorted by relevance
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8 // RUN: %clang -cc1 -include-pch %t -emit-llvm -o - %s | FileCheck -check-prefix=IR %s15 // CHECK-IR: define void @all() nounwind 16 // CHECK-IR: {{call.*objc_msgSend}}17 // CHECK-IR: {{call.*objc_msgSend}}18 // CHECK-IR: {{call.*objc_msgSend}}19 // CHECK-IR: {{call.*objc_msgSend}}20 // CHECK-IR: ret void
4 // RUN: %clang -cc1 -include-pch %t -emit-llvm -o - %s | FileCheck -check-prefix=IR %s40 // CHECK-IR: define internal void @test_numeric_literals()43 // CHECK-IR: {{call.*17}}46 // CHECK-IR: {{call.*1.745}}
4 …cc1 -include-pch %t -x objective-c++ -std=c++0x -emit-llvm -o - %s | FileCheck -check-prefix=IR %s51 // CHECK-IR: define linkonce_odr void @_Z29variadic_dictionary_expansionIJP8NSStringS1_EJP8NSNumber…55 // CHECK-IR: {{call.*objc_msgSend}}56 // CHECK-IR: ret void
17 ir.h for the IR structures.35 7) The driver performs code generation out of the IR, taking a linked37 ir_to_mesa.cpp for Mesa IR code generation.41 Q: What is HIR versus IR versus LIR?44 high-level IR ("HIR"), with things like matrix operations, structure49 producing a low level IR ("LIR").54 accesses, and matrix multiplication broken down. The Mesa IR backend57 shader IR backend could potentially even handle some matrix operations58 without breaking them down, but the 965 fragment shader IR backend61 low-level IR that will make everyone happy. So that usage has fallen[all …]
62 137714 vx1787 x86/amd64->IR: 0x66 0xF 0xF7 0xC6 (maskmovq, maskmovdq)81 147498 vx1795 amd64->IR: 0xF0 0xF 0xB0 0xF (lock cmpxchg %cl,(%rdi))89 148363 marginal amd64->IR: 0x65 0x4C 0x8B 0x1C (mov %gs:0x10,%r11)95 149838 marginal x86->IR: 0xF 0xAE 0xD 0xE0 (FXRSTOR ?)119 152501 vx1800 vex x86->IR: 0x27 0x66 0x89 0x45 (daa) 120 152818 vx1801 vex x86->IR: 0xF3 0xAC 0xFC 0x9C (rep lodsb)176 vx1737 vx1752 32 n-i-bz x86->IR: 26 2E 64 65 90 %es:%cs:%fs:%gs:nop289 pending pending s93 133962 amd64->IR: 0xF2 0x4C 0xF 0x10 (rex64X ...)291 pending pending s93 135023 amd64->IR: 0x49 0xDD 0x86 0xE0 317 pending pending 135264 ppc->IR: dcbzl instruction missing[all …]
30 vx1604 fixed 124499 amd64->IR: 0xF 0xE 0x48 0x85 (femms)32 wontfix 124697 vex x86->IR: 0xF 0x70 0xC9 0x0 (pshufw)33 vx1603 fixed 124892 vex x86->IR: 0xF3 0xAE (REPx SCASB)37 vx1602 fixed n-i-bz amd64->IR: 0x66 0xF 0xF5 (pmaddwd)43 vx1612 fixed 125607 amd64->IR: 0x66 0xF 0xA3 0x2 (btw etc)44 vx1613 fixed 125651 amd64->IR: 0xF8 0x49 0xFF 0xE3 (clc?)56 vx1611 fixed 126243 vex x86->IR: popw mem57 low 125265 vex x86->IR: 0xD9 0xD0 (fnop)58 low 126257 vex x86->IR: 0xF2 0x0F 0xF0 0x40 (lddqu) (sse3)59 low 126258 vex x86->IR: 0xDF 0x4D (fisttp) (sse3)[all …]
112 113015 vex amd64->IR: 0xE3 0x14 0x48 0x83 (jrcxz)153 113851 vex x86->IR: (pmaddwd): 0x66 0xF 0xF5 0xC7163 114412 vex amd64->IR: 0xF 0xAD 0xC2 0xD3 (128-bit shift, shrdq?)168 114455 vex amd64->IR: 0xF 0xAC 0xD0 0x1 (also shrdq)173 115590: amd64->IR: 0x67 0xE3 0x9 0xEB (address size override)228 111724 vex amd64->IR: unhandled instruction bytes: 0x41 0xF 0xAB243 111748 vex amd64->IR: unhandled instruction bytes: fucom 256 111829 vex x86->IR: unhandled instruction bytes: sbb Al, Ib262 111851 vex x86->IR: unhandled instruction bytes: 0x9F 0x89289 112501 vex x86->IR: movq (0xF 0x7F 0xC1 0xF) (mmx MOVQ)[all …]
41 126255 Wont pend vex x86->IR: 0xDF 0x75 (fbstp) (x87 BCD stores)126 167700 HIGH,WF pend vex x86->IR: unhandled instruction bytes: 0xD5 0x36 0x5B225 172417 Fixd vx1867 x86->IR: 0x82 ...227 172563 Fixd vx???? amd64->IR: 0xD9 0xF5 - fprem1234 173751 Fixd vx1876 amd64->IR: 0x48 0xF 0x6F 0x45237 174532 WF DUP amd64->IR: 0x48 0xF 0xED 0x0 244 175150 Fixd vx1873 x86->IR: 0xF2 0xF 0x11 0xC1 (movss xmm1, xmm0)281 vx1836/7 vx1845 Vfd 126389 vex x86->IR: 0xF 0xAE (FXRSTOR)284 vx1838 vx1846 Vfd 152818 vex x86->IR: 0xF3 0xAC (repz lodsb) 286 vx1834 vx1843 Vfd 153196 vex x86->IR: 0xF2 0xA6 (repnz cmpsb) [all …]
57 188127 vex amd64->IR: unhandled instruction bytes: 0xF0 0xF 0xB0 0xA107 189737 vex amd64->IR: unhandled instruction bytes: 0xAC (lods)
7 .IR type ,8 .IR type10 .IR code ,
7 .IR type ,8 .IR type
10 .IR filename ".\|.\|."15 .IR filename ".\|.\|."20 .IR filename ".\|.\|."22 .IR Bzgrep
26 .IR diff "."30 .IR file1 ".bz2."34 .IR diff "."
8 # Name: "Fake" Unicode to ISO-IR-165 table11 # This is not a real ISO-IR-165 table, but a "fake" table to return U+FFFD12 # for every byte sequence valid in ISO-IR-165. Chrome and Android
134 DeltaTreeInteriorNode(const InsertResult &IR) in DeltaTreeInteriorNode() argument136 Children[0] = IR.LHS; in DeltaTreeInteriorNode()137 Children[1] = IR.RHS; in DeltaTreeInteriorNode()138 Values[0] = IR.Split; in DeltaTreeInteriorNode()139 FullDelta = IR.LHS->getFullDelta()+IR.RHS->getFullDelta()+IR.Split.Delta; in DeltaTreeInteriorNode()
49 write API doc, clarify IR semantics51 make IR utils module
31 # because it breaks this up into non-atomic IR. This non atomic IR restores PC
167 268621 s390x: improve IR generation for XC171 269078 arm->IR: unhandled instruction SUB (SP minus immediate/register) 210 272893 amd64->IR: 0x66 0xF 0x38 0x2B 0xC1 0x66 0xF 0x7F == (closed as dup)214 273318 amd64->IR: 0x66 0xF 0x3A 0x61 0xC1 0x38 (missing PCMPxSTRx case)215 273318 unhandled PCMPxSTRx case: vex amd64->IR: 0x66 0xF 0x3A 0x61 0xC1 0x38 225 274776 amd64->IR: 0x66 0xF 0x38 0x2B 0xC5 0x66267 280290 vex amd64->IR: 0x66 0xF 0x38 0x28 0xC1 0x66 0xF 0x6F283 283000 vex amd64->IR: 0x66 0xF 0x3A 0xA 0xC0 0x9 0xF3 0xF322 194402 vex amd64->IR: 0x48 0xF 0xAE 0x4 (proper FX{SAVE,RSTOR} support)323 210481 vex amd64->IR: Assertion `sz == 2 || sz == 4' failed (REX.W POPQ)[all …]
22 could be faster, because we are using a "smarter" IR (SSA based).26 > Optimization code is usually heavily tied in to the specific IR they use.28 Understood. The only reason that I brought this up is because SGI's IR is
4 Subject: lowering the IR6 BTW, I do think that we should consider lowering the IR as you said. I
25 The risk is that this sounds like a universal IR -- something that the28 convince anyone that we have a universal IR that will work. We need to
219 am->Aam.IR.imm = imm32; in AMD64AMode_IR()220 am->Aam.IR.reg = reg; in AMD64AMode_IR()249 if (am->Aam.IR.imm == 0) in ppAMD64AMode()252 vex_printf("0x%x(", am->Aam.IR.imm); in ppAMD64AMode()253 ppHRegAMD64(am->Aam.IR.reg); in ppAMD64AMode()271 addHRegUse(u, HRmRead, am->Aam.IR.reg); in addRegUsage_AMD64AMode()285 am->Aam.IR.reg = lookupHRegRemap(m, am->Aam.IR.reg); in mapRegs_AMD64AMode()2126 if (am->Aam.IR.imm == 0 in doAMode_M()2127 && am->Aam.IR.reg != hregAMD64_RSP() in doAMode_M()2128 && am->Aam.IR.reg != hregAMD64_RBP() in doAMode_M()[all …]
164 am->Xam.IR.imm = imm32; in X86AMode_IR()165 am->Xam.IR.reg = reg; in X86AMode_IR()182 return X86AMode_IR( am->Xam.IR.imm, am->Xam.IR.reg ); in dopyX86AMode()194 if (am->Xam.IR.imm == 0) in ppX86AMode()197 vex_printf("0x%x(", am->Xam.IR.imm); in ppX86AMode()198 ppHRegX86(am->Xam.IR.reg); in ppX86AMode()216 addHRegUse(u, HRmRead, am->Xam.IR.reg); in addRegUsage_X86AMode()230 am->Xam.IR.reg = lookupHRegRemap(m, am->Xam.IR.reg); in mapRegs_X86AMode()1831 if (am->Xam.IR.imm == 0 in doAMode_M()1832 && am->Xam.IR.reg != hregX86_ESP() in doAMode_M()[all …]
58 #define PUSH(Y,IL,IR,IPL,IPR,FL) { stack[StIn].y=(ushort)(Y); \ argument60 stack[StIn].r=(ushort)(IR); \66 #define POP(Y,IL,IR,IPL,IPR,FL) { StIn--; \ argument69 IR=stack[StIn].r;\
22 ; The IR type <4 x i32> is ignored.