| /external/llvm/lib/Target/ |
| D | TargetInstrInfo.cpp | 35 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
37 return TRI->getPointerRegClass(RegClass); in getRegClass()
40 if (RegClass < 0) in getRegClass()
44 return TRI->getRegClass(RegClass); in getRegClass()
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterScavenging.h | 111 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
122 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
124 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister() argument
125 return scavengeRegister(RegClass, MBBI, SPAdj); in scavengeRegister()
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| D | MachineRegisterInfo.h | 293 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrArithmetic.td | 552 /// RegClass - This is the register class associated with this type. For
554 RegisterClass RegClass = regclass;
646 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
653 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
654 [(set typeinfo.RegClass:$dst,
655 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
664 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
671 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
672 [(set typeinfo.RegClass:$dst, EFLAGS,
673 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.h | 41 OwningArrayPtr<RCInfo> RegClass; variable
65 const RCInfo &RCI = RegClass[RC->getID()]; in get()
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| D | MachineRegisterInfo.cpp | 98 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ in createVirtualRegister() argument
99 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
100 assert(RegClass->isAllocatable() && in createVirtualRegister()
110 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
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| D | RegisterClassInfo.cpp | 41 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
75 RCInfo &RCI = RegClass[RC->getID()]; in compute()
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 61 int16_t RegClass;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1455 SDValue RegClass = in PairSRegs() local
1459 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in PairSRegs()
1467 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32); in PairDRegs() local
1470 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in PairDRegs()
1478 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); in PairQRegs() local
1481 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in PairQRegs()
1490 SDValue RegClass = in QuadSRegs() local
1496 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in QuadSRegs()
1506 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); in QuadDRegs() local
1511 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in QuadDRegs()
[all …]
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| /external/llvm/utils/TableGen/ |
| D | CodeGenDAGPatterns.cpp | 1252 Record *RegClass = R->getValueAsDef("RegClass"); in getImplicitType() local
1254 return EEVT::TypeSet(T.getRegisterClass(RegClass).getValueTypes()); in getImplicitType()
1540 Record *RegClass = ResultNode->getValueAsDef("RegClass"); in ApplyTypeConstraints() local
1542 CDP.getTargetInfo().getRegisterClass(RegClass); in ApplyTypeConstraints()
1603 Record *RegClass = OperandNode->getValueAsDef("RegClass"); in ApplyTypeConstraints() local
1605 CDP.getTargetInfo().getRegisterClass(RegClass); in ApplyTypeConstraints()
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| D | CodeGenRegisters.cpp | 961 CodeGenRegisterClass *RegClass = RegBank.getRegClasses()[i]; in computeUberSets() local
962 if (!RegClass->Allocatable) in computeUberSets()
965 const CodeGenRegister::Set &Regs = RegClass->getMembers(); in computeUberSets()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 269 unsigned &RegClass, unsigned &Cost) { in GetCostForDef() argument
281 RegClass = RC->getID(); in GetCostForDef()
289 RegClass = RC->getID(); in GetCostForDef()
294 RegClass = TLI->getRepRegClassFor(VT)->getID(); in GetCostForDef()
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| /external/llvm/include/llvm/Target/ |
| D | Target.td | 155 // dags: (RegClass SubRegIndex, SubRegindex, ...)
545 // RegClass - The register class of the operand.
546 RegisterClass RegClass = regclass;
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 582 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { in AddThumb1SBit()
|