| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCallingConvLower.h | 111 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { in getFirstUnallocated() argument
113 if (!isAllocated(Regs[i])) in getFirstUnallocated()
138 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { in AllocateReg() argument
139 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); in AllocateReg()
144 unsigned Reg = Regs[FirstUnalloc]; in AllocateReg()
150 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, in AllocateReg() argument
152 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); in AllocateReg()
157 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; in AllocateReg()
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| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 134 const CodeGenRegister::Set &Regs = RC.getMembers(); in EmitRegUnitPressure() local
135 if (Regs.empty()) in EmitRegUnitPressure()
140 OS << " {" << (*Regs.begin())->getWeight(RegBank) in EmitRegUnitPressure()
199 const std::vector<CodeGenRegister*> &Regs, in EmitRegMappingTables() argument
207 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in EmitRegMappingTables()
208 Record *Reg = Regs[i]->TheDef; in EmitRegMappingTables()
226 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace"); in EmitRegMappingTables()
274 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in EmitRegMappingTables()
275 Record *Reg = Regs[i]->TheDef; in EmitRegMappingTables()
325 const std::vector<CodeGenRegister*> &Regs, in EmitRegMapping() argument
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| D | CodeGenRegisters.cpp | 100 RegUnitIterator(const CodeGenRegister::Set &Regs): in RegUnitIterator() argument
101 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() { in RegUnitIterator()
759 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local
760 std::sort(Regs.begin(), Regs.end(), LessRecord()); in CodeGenRegBank()
761 Registers.reserve(Regs.size()); in CodeGenRegBank()
763 for (unsigned i = 0, e = Regs.size(); i != e; ++i) in CodeGenRegBank()
764 getReg(Regs[i]); in CodeGenRegBank()
934 CodeGenRegister::Set Regs; member
965 const CodeGenRegister::Set &Regs = RegClass->getMembers(); in computeUberSets() local
966 if (Regs.empty()) in computeUberSets()
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| D | RegisterInfoEmitter.h | 52 const std::vector<CodeGenRegister*> &Regs, bool isCtor);
54 const std::vector<CodeGenRegister*> &Regs,
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| D | CodeGenTarget.cpp | 197 const std::vector<CodeGenRegister*> &Regs = getRegBank().getRegisters(); in getRegisterByName() local
198 for (unsigned i = 0, e = Regs.size(); i != e; ++i) in getRegisterByName()
199 if (Regs[i]->TheDef->getValueAsString("AsmName") == Name) in getRegisterByName()
200 return Regs[i]; in getRegisterByName()
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| D | CodeGenRegisters.h | 504 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
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| D | AsmMatcherEmitter.cpp | 1822 const std::vector<CodeGenRegister*> &Regs = in EmitMatchRegisterName() local
1824 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in EmitMatchRegisterName()
1825 const CodeGenRegister *Reg = Regs[i]; in EmitMatchRegisterName()
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 232 unsigned getFirstUnallocated(const uint16_t *Regs, unsigned NumRegs) const { in getFirstUnallocated() argument
234 if (!isAllocated(Regs[i])) in getFirstUnallocated()
259 unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) { in AllocateReg() argument
260 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); in AllocateReg()
265 unsigned Reg = Regs[FirstUnalloc]; in AllocateReg()
271 unsigned AllocateReg(const uint16_t *Regs, const uint16_t *ShadowRegs, in AllocateReg() argument
273 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); in AllocateReg()
278 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; in AllocateReg()
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| D | RegisterScavenging.h | 146 void setUsed(BitVector &Regs) { in setUsed() argument
147 RegsAvailable.reset(Regs); in setUsed()
149 void setUnused(BitVector &Regs) { in setUnused() argument
150 RegsAvailable |= Regs; in setUnused()
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| D | MachineRegisterInfo.h | 351 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } in addPhysRegsUsed() argument
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 578 SmallVector<std::pair<unsigned,bool>, 4> Regs; in emitPushInst() local
610 Regs.push_back(std::make_pair(Reg, isKill)); in emitPushInst()
613 if (Regs.empty()) in emitPushInst()
615 if (Regs.size() > 1 || StrOpc== 0) { in emitPushInst()
619 for (unsigned i = 0, e = Regs.size(); i < e; ++i) in emitPushInst()
620 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); in emitPushInst()
621 } else if (Regs.size() == 1) { in emitPushInst()
624 .addReg(Regs[0].first, getKillRegState(Regs[0].second)) in emitPushInst()
629 Regs.clear(); in emitPushInst()
648 SmallVector<unsigned, 4> Regs; in emitPopInst() local
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| D | ARMLoadStoreOptimizer.cpp | 97 ArrayRef<std::pair<unsigned, bool> > Regs,
287 ArrayRef<std::pair<unsigned, bool> > Regs, in MergeOps()
290 unsigned NumRegs = Regs.size(); in MergeOps()
320 NewBase = Regs[NumRegs-1].first; in MergeOps()
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) in MergeOps()
354 | getKillRegState(Regs[i].second)); in MergeOps()
393 SmallVector<std::pair<unsigned, bool>, 8> Regs; in MergeOpsUpdate() local
400 Regs.push_back(std::make_pair(Reg, isKill)); in MergeOpsUpdate()
416 Pred, PredReg, Scratch, dl, Regs, ImpDefs)) in MergeOpsUpdate()
423 if (Regs[i-memOpsBegin].second) { in MergeOpsUpdate()
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| D | Thumb2SizeReduction.cpp | 192 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) in HasImplicitCPSRDef() local
193 if (*Regs == ARM::CPSR) in HasImplicitCPSRDef()
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| /external/llvm/lib/CodeGen/ |
| D | ExecutionDepsFix.cpp | 575 SmallVector<LiveReg, 4> Regs; in visitSoftInstr() local
586 for (SmallVector<LiveReg, 4>::iterator i = Regs.begin(), e = Regs.end(); in visitSoftInstr()
590 Regs.insert(i, LR); in visitSoftInstr()
594 Regs.push_back(LR); in visitSoftInstr()
600 while (!Regs.empty()) { in visitSoftInstr()
602 dv = Regs.pop_back_val().Value; in visitSoftInstr()
609 DomainValue *Latest = Regs.pop_back_val().Value; in visitSoftInstr()
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| D | AggressiveAntiDepBreaker.cpp | 71 std::vector<unsigned> &Regs, in GetGroupRegs() argument
76 Regs.push_back(Reg); in GetGroupRegs()
558 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
559 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); in FindSuitableFreeRegisters()
560 assert(Regs.size() > 0 && "Empty register group!"); in FindSuitableFreeRegisters()
561 if (Regs.size() == 0) in FindSuitableFreeRegisters()
571 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
572 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
591 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
592 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
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| D | LocalStackSlotAllocation.cpp | 197 lookupCandidateBaseReg(const SmallVector<std::pair<unsigned, int64_t>, 8> &Regs, in lookupCandidateBaseReg() argument
203 unsigned e = Regs.size(); in lookupCandidateBaseReg()
205 RegOffset = Regs[i]; in lookupCandidateBaseReg()
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| D | AggressiveAntiDepBreaker.h | 97 std::vector<unsigned> &Regs,
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| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 798 SmallPtrSet<const SCEV *, 16> &Regs,
810 SmallPtrSet<const SCEV *, 16> &Regs,
814 SmallPtrSet<const SCEV *, 16> &Regs,
824 SmallPtrSet<const SCEV *, 16> &Regs, in RateRegister() argument
846 if (!Regs.count(AR->getOperand(1))) { in RateRegister()
847 RateRegister(AR->getOperand(1), Regs, L, SE, DT); in RateRegister()
872 SmallPtrSet<const SCEV *, 16> &Regs, in RatePrimaryRegister() argument
880 if (Regs.insert(Reg)) { in RatePrimaryRegister()
881 RateRegister(Reg, Regs, L, SE, DT); in RatePrimaryRegister()
888 SmallPtrSet<const SCEV *, 16> &Regs, in RateFormula() argument
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 577 SmallVector<unsigned, 4> Regs; member
583 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} in RegsForValue()
594 Regs.push_back(Reg + i); in RegsForValue()
614 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); in append()
669 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); in getCopyFromRegs()
671 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); in getCopyFromRegs()
680 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || in getCopyFromRegs()
685 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); in getCopyFromRegs()
742 unsigned NumRegs = Regs.size(); in getCopyToRegs()
759 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); in getCopyToRegs()
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| /external/llvm/include/llvm/Target/ |
| D | Target.td | 239 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
243 list<dag> SubRegs = Regs;
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 2159 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, in CreateRegList() argument
2163 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) in CreateRegList()
2166 contains(Regs.front().first)) in CreateRegList()
2171 I = Regs.begin(), E = Regs.end(); I != E; ++I) in CreateRegList()
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| /external/webkit/PerformanceTests/Parser/resources/ |
| D | final-url-en | 55170 http://www.marcorsyscom.usmc.mil/sites/mcub/PAGES/Uniform%20Regs%20Chapters/Chapter%2010%5CChapter%…
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