| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| D | RegOps.java | 115 public static final int SHL = 23; field in RegOps
336 case SHL: return "shl"; in opName()
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| D | DexTranslationAdvice.java | 88 case RegOps.SHL: in hasConstantOperation()
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| D | Rops.java | 339 new Rop(RegOps.SHL, Type.INT, StdTypeList.INT_INT, "shl-int");
343 new Rop(RegOps.SHL, Type.LONG, StdTypeList.LONG_INT, "shl-long");
484 new Rop(RegOps.SHL, Type.INT, StdTypeList.INT, "shl-const-int");
488 new Rop(RegOps.SHL, Type.LONG, StdTypeList.INT, "shl-const-long");
1147 case RegOps.SHL: return opShl(sources); in ropFor()
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUNodes.td | 86 // Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only):
87 def SPUvec_shl: SDNode<"ISD::SHL", SPUvecshift_type, []>;
105 // SHL_BITS the same as SHL for i128, but ISD::SHL is not implemented for i128
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| /external/openssl/crypto/bn/asm/ |
| D | ppc.pl | 120 $SHL= "slw"; # shift left
144 $SHL= "sld"; # shift left
1648 $SHL r3,r3,r7 # h = (h<< i)
1650 $SHL r5,r5,r7 # d<<=i
1652 $SHL r4,r4,r7 # l <<=i
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 345 if (Opcode == ISD::SHL) { in isRotateAndMask()
396 if (Op0.getOperand(0).getOpcode() == ISD::SHL || in SelectBitfieldInsert()
398 if (Op1.getOperand(0).getOpcode() != ISD::SHL && in SelectBitfieldInsert()
405 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { in SelectBitfieldInsert()
406 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && in SelectBitfieldInsert()
418 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && in SelectBitfieldInsert()
421 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; in SelectBitfieldInsert()
425 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && in SelectBitfieldInsert()
428 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; in SelectBitfieldInsert()
977 case ISD::SHL: { in Select()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 71 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; in PromoteIntegerResult()
534 return DAG.getNode(ISD::SHL, N->getDebugLoc(), in PromoteIntRes_SHL()
723 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, in PromoteIntRes_VAARG()
790 case ISD::SHL: in PromoteIntegerOperand()
895 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, in PromoteIntOp_BUILD_PAIR()
1156 case ISD::SHL: in ExpandIntegerResult()
1273 if (N->getOpcode() == ISD::SHL) { in ExpandShiftByConstant()
1278 Hi = DAG.getNode(ISD::SHL, DL, in ExpandShiftByConstant()
1293 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy)); in ExpandShiftByConstant()
1295 DAG.getNode(ISD::SHL, DL, NVT, InH, in ExpandShiftByConstant()
[all …]
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| D | DAGCombiner.cpp | 1113 case ISD::SHL: return visitSHL(N); in visit()
1192 case ISD::SHL: in combine()
1350 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, in combineShlAddConstant()
1352 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, in combineShlAddConstant()
1469 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { in visitADD()
1473 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { in visitADD()
1479 if (N1.getOpcode() == ISD::SHL && in visitADD()
1485 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, in visitADD()
1488 if (N0.getOpcode() == ISD::SHL && in visitADD()
1494 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, in visitADD()
[all …]
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| D | TargetLowering.cpp | 1439 case ISD::SHL: in SimplifyDemandedBits()
1455 unsigned Opc = ISD::SHL; in SimplifyDemandedBits()
1481 isTypeDesirableForOp(ISD::SHL, InnerVT)) { in SimplifyDemandedBits()
1486 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, in SimplifyDemandedBits()
1515 if (InOp.getOpcode() == ISD::SHL && in SimplifyDemandedBits()
1523 Opc = ISD::SHL; in SimplifyDemandedBits()
1608 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, in SimplifyDemandedBits()
1822 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, in SimplifyDemandedBits()
1898 if (Val.getOpcode() == ISD::SHL) in ValueHasExactlyOneBitSet()
2516 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1, in SimplifySetCC()
[all …]
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| D | LegalizeDAG.cpp | 549 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); in ExpandUnalignedLoad()
824 case ISD::SHL: in LegalizeOp()
1046 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, in LegalizeOp()
1076 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, in LegalizeOp()
1502 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, in ExpandFCOPYSIGN()
2298 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); in ExpandBSWAP()
2302 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); in ExpandBSWAP()
2303 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); in ExpandBSWAP()
2312 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); in ExpandBSWAP()
2313 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); in ExpandBSWAP()
[all …]
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| D | FastISel.cpp | 955 return SelectBinaryOp(I, ISD::SHL); in SelectOperator()
1112 Opcode = ISD::SHL; in FastEmit_ri_()
1122 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) && in FastEmit_ri_()
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| /external/v8/src/ |
| D | token.h | 99 T(SHL, "<<", 11) \
269 return (SHL <= op) && (op <= SHR); in IsShiftOp()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 26 case ISD::SHL: return ARM_AM::lsl; in getShiftOpcForNode()
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| /external/openssl/crypto/sha/asm/ |
| D | sha512-ppc.pl | 46 $SHL="sldi";
54 $SHL="slwi";
187 $SHL $num,$num,`log(16*$SZ)/log(2)`
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| /external/llvm/test/Transforms/InstCombine/ |
| D | pr8547.ll | 2 ; Converting the 2 shifts to SHL 6 without the AND is wrong. PR 8547.
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 96 setOperationAction(ISD::SHL, MVT::i8, Custom); in MSP430TargetLowering()
99 setOperationAction(ISD::SHL, MVT::i16, Custom); in MSP430TargetLowering()
183 case ISD::SHL: // FALLTHROUGH in LowerOperation()
597 case ISD::SHL: in LowerShifts()
598 return DAG.getNode(MSP430ISD::SHL, dl, in LowerShifts()
623 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA), in LowerShifts()
979 case MSP430ISD::SHL: return "MSP430ISD::SHL"; in getTargetNodeName()
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| D | MSP430ISelLowering.h | 65 SHL, SRA, SRL enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 310 SHL, SRA, SRL, ROTL, ROTR, enumerator
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| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| D | SCCP.java | 437 case RegOps.SHL: in simulateMath()
516 case RegOps.SHL: in simulateStmt()
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| /external/speex/libspeex/ |
| D | arch.h | 178 #define SHL(a,shift) (a) macro
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| D | fixed_generic.h | 60 #define SHL(a,shift) ((spx_word32_t)(a) << (shift)) macro
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| /external/v8/src/ia32/ |
| D | code-stubs-ia32.cc | 1261 case Token::SHL: in GenerateSmiCode()
1299 case Token::SHL: in GenerateSmiCode()
1430 case Token::SHL: in GenerateSmiCode()
1445 case Token::SHL: in GenerateSmiCode()
1473 case Token::SHL: in GenerateSmiCode()
1489 ASSERT_EQ(Token::SHL, op_); in GenerateSmiCode()
1572 case Token::SHL: in GenerateSmiCode()
1607 case Token::SHL: in GenerateSmiStub()
1634 case Token::SHL: in GenerateSmiStub()
1755 case Token::SHL: in GenerateInt32Stub()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 765 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount); in FoldMaskAndShiftToExtract()
791 if (Shift.getOpcode() != ISD::SHL || in FoldMaskedShiftToScaledMask()
810 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1)); in FoldMaskedShiftToScaledMask()
917 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt); in FoldMaskAndShiftToScale()
991 case ISD::SHL: in MatchAddressRecursively()
1214 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break; in MatchAddressRecursively()
1996 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse()) in Select()
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| D | X86ISelLowering.cpp | 746 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); in X86TargetLowering()
986 setOperationAction(ISD::SHL, MVT::v8i16, Custom); in X86TargetLowering()
987 setOperationAction(ISD::SHL, MVT::v16i8, Custom); in X86TargetLowering()
996 setOperationAction(ISD::SHL, MVT::v2i64, Legal); in X86TargetLowering()
997 setOperationAction(ISD::SHL, MVT::v4i32, Legal); in X86TargetLowering()
1004 setOperationAction(ISD::SHL, MVT::v2i64, Custom); in X86TargetLowering()
1005 setOperationAction(ISD::SHL, MVT::v4i32, Custom); in X86TargetLowering()
1054 setOperationAction(ISD::SHL, MVT::v16i16, Custom); in X86TargetLowering()
1055 setOperationAction(ISD::SHL, MVT::v32i8, Custom); in X86TargetLowering()
1095 setOperationAction(ISD::SHL, MVT::v4i64, Legal); in X86TargetLowering()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 687 if (Shl.getOpcode() != ISD::SHL) in PerformORCombine()
1800 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); in LowerFCOPYSIGN32()
1803 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); in LowerFCOPYSIGN32()
1847 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); in LowerFCOPYSIGN64()
1857 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, in LowerFCOPYSIGN64()
1888 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); in LowerFABS32()
1913 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); in LowerFABS64()
2201 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal, in WriteByValArg()
2220 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword, in WriteByValArg()
2303 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i64, LoadVal, in PassByValArg64()
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