| /external/llvm/test/CodeGen/X86/ |
| D | rounding-ops.ll | 1 ; RUN: llc < %s -march=x86-64 -mattr=+sse41 | FileCheck -check-prefix=CHECK-SSE %s
8 ; CHECK-SSE: test1:
9 ; CHECK-SSE: roundss $1
21 ; CHECK-SSE: test2:
22 ; CHECK-SSE: roundsd $1
34 ; CHECK-SSE: test3:
35 ; CHECK-SSE: roundss $12
47 ; CHECK-SSE: test4:
48 ; CHECK-SSE: roundsd $12
60 ; CHECK-SSE: test5:
[all …]
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| D | nosse-error1.ll | 3 ; RUN: grep "SSE register return with SSE disabled" %t2
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| D | nosse-error2.ll | 3 ; RUN: grep "SSE register return with SSE disabled" %t2
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| D | vec_insert-7.ll | 3 ; (Without SSE they are split to two ints, and the code is much better.)
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| /external/libvpx/vp8/encoder/ppc/ |
| D | csystemdependent.c | 52 …c_ptr, int source_stride, unsigned char *ref_ptr, int recon_stride, unsigned int *SSE, int *Sum);
53 …c_ptr, int source_stride, unsigned char *ref_ptr, int recon_stride, unsigned int *SSE, int *Sum);
61 …c_ptr, int source_stride, unsigned char *ref_ptr, int recon_stride, unsigned int *SSE, int *Sum);
92 …c_ptr, int source_stride, unsigned char *ref_ptr, int recon_stride, unsigned int *SSE, int *Sum);
93 …c_ptr, int source_stride, unsigned char *ref_ptr, int recon_stride, unsigned int *SSE, int *Sum);
124 …c_ptr, int source_stride, unsigned char *ref_ptr, int recon_stride, unsigned int *SSE, int *Sum);
125 …c_ptr, int source_stride, unsigned char *ref_ptr, int recon_stride, unsigned int *SSE, int *Sum);
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| /external/libvpx/vp8/encoder/ |
| D | variance_c.c | 71 unsigned int *SSE, in vp8_get8x8var_c() argument
76 variance(src_ptr, source_stride, ref_ptr, recon_stride, 8, 8, SSE, Sum); in vp8_get8x8var_c()
77 return (*SSE - (((*Sum) * (*Sum)) >> 6)); in vp8_get8x8var_c()
87 unsigned int *SSE, in vp8_get16x16var_c() argument
92 variance(src_ptr, source_stride, ref_ptr, recon_stride, 16, 16, SSE, Sum); in vp8_get16x16var_c()
93 return (*SSE - (((*Sum) * (*Sum)) >> 8)); in vp8_get16x16var_c()
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| /external/oprofile/events/i386/atom/ |
| D | unit_masks | 10 0x01 prefetcht0 Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed
11 0x06 sw_l2 Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed
12 0x08 prefetchnta Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed
85 0x01 packed_single Retired Streaming SIMD Extensions (SSE) packed-single instructions
86 0x02 scalar_single Retired Streaming SIMD Extensions (SSE) scalar-single instructions
92 0x01 packed_single Retired computational Streaming SIMD Extensions (SSE) packed-single instructions
93 0x02 scalar_single Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions
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| D | events | 15 …1 um:simd_prefetch minimum:6000 name:PREFETCH : Streaming SIMD Extensions (SSE) Prefetch instructi…
71 …_retired minimum:6000 name:SIMD_INST_RETIRED : Retired Streaming SIMD Extensions (SSE) instructions
73 …0 name:SIMD_COMP_INST_RETIRED : Retired computational Streaming SIMD Extensions (SSE) instructions.
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| /external/llvm/lib/Target/X86/ |
| D | X86.td | 40 "Enable SSE instructions",
41 // SSE codegen depends on cmovs, and all
54 "Enable SSE 4.1 instructions",
57 "Enable SSE 4.2 instructions",
80 "Support SSE 4a instructions",
174 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
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| D | README-SSE.txt | 2 // Random ideas for the X86 backend: SSE-specific stuff.
7 SSE Variable shift can be custom lowered to something like this, which uses a
22 SSE has instructions for doing operations on complex numbers, we should pattern
72 When compiled with unsafemath enabled, "main" should enable SSE DAZ mode and
73 other fast SSE modes.
77 Think about doing i64 math in SSE regs on x86-32.
81 This testcase should have no SSE instructions in it, and only one load from
96 SSE should implement 'select_cc' using 'emulated conditional moves' that use
126 Lower memcpy / memset to a series of SSE 128 bit move instructions when it's
135 when using SSE.
[all …]
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| D | X86InstrFormats.td | 85 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
289 // SI - SSE 1 & 2 scalar instructions
300 // SIi8 - SSE 1 & 2 scalar instructions
311 // PI - SSE 1 & 2 packed instructions
322 // PIi8 - SSE 1 & 2 packed instructions with immediate
440 // SS48I - SSE 4.1 instructions with T8 prefix.
441 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
454 // SS428I - SSE 4.2 instructions with T8 prefix.
460 // SS42FI - SSE 4.2 instructions with T8XD prefix.
465 // SS42AI = SSE 4.2 instructions with TA prefix
[all …]
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| D | X86InstrFragmentsSIMD.td | 22 // SSE specific DAG Nodes.
170 // SSE Complex Patterns
174 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
197 // SSE pattern fragments
263 // memory operands in most SSE instructions, which are required to
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| /external/oprofile/events/x86-64/family10/ |
| D | unit_masks | 50 0x01 Add pipe ops excluding load ops and SSE move ops
51 0x02 Multiply pipe ops excluding load ops and SSE move ops
52 0x04 Store pipe ops excluding load ops and SSE move ops
53 0x08 Add pipe load ops and SSE move ops
54 0x10 Multiply pipe load ops and SSE move ops
55 0x20 Store pipe load ops and SSE move ops
68 0x04 SSE instructions (SSE, SSE2, SSE3, and SSE4A)
75 0x02 SSE retype microfaults
76 0x04 SSE reclass microfaults
77 0x08 SSE and x87 microtraps
[all …]
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| /external/oprofile/events/i386/core/ |
| D | unit_masks | 41 0x00 SSE Packed Single
42 0x01 SSE Scalar-Single
67 0x03 SSE streaming store instructions
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| /external/libvpx/vp8/encoder/x86/ |
| D | variance_mmx.c | 44 unsigned int *SSE,
53 unsigned int *SSE,
93 unsigned *SSE, in vp8_get16x16var_mmx() argument
109 *SSE = var; in vp8_get16x16var_mmx()
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| D | variance_sse2.c | 39 unsigned int *SSE,
53 unsigned int *SSE,
69 unsigned int *SSE,
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| D | variance_ssse3.c | 22 unsigned int *SSE,
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| /external/qemu/target-i386/ |
| D | TODO | 17 - SSE alignment checks
18 - fix SSE min/max with nans
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| /external/oprofile/events/i386/p6_mobile/ |
| D | unit_masks | 24 0x00 SSE Packed Single
25 0x01 SSE Scalar-Single
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| /external/oprofile/events/x86-64/hammer/ |
| D | unit_masks | 57 0x04 Combined packed SSE & SSE2 instructions
58 0x08 Combined packed scalar SSE & SSE2 instructions
65 0x02 SSE retype microfaults
66 0x04 SSE reclass microfaults
67 0x08 SSE and x87 microtraps
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| /external/oprofile/events/i386/core_2/ |
| D | unit_masks | 36 0x03 SSE weakly-ordered stores
162 0x01 Retired SSE packed-single instructions
163 0x02 Retired SSE scalar-single instructions
169 0x01 Retired computational SSE packed-single instructions
170 0x02 Retired computational SSE scalar-single instructions
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| /external/oprofile/events/x86-64/family11h/ |
| D | unit_masks | 63 0x04 Packed SSE & SSE2 instructions
64 0x08 Packed scalar SSE & SSE2 instructions
71 0x02 SSE retype microfaults
72 0x04 SSE reclass microfaults
73 0x08 SSE and x87 microtraps
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| /external/clang/lib/CodeGen/ |
| D | TargetInfo.cpp | 854 SSE, enumerator
1093 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp)) in postMerge()
1095 if (Hi == SSEUp && Lo != SSE) in postMerge()
1096 Hi = SSE; in postMerge()
1136 return SSE; in merge()
1165 Current = SSE; in classify()
1219 Current = SSE; in classify()
1233 Lo = SSE; in classify()
1249 Current = SSE; in classify()
1251 Lo = Hi = SSE; in classify()
[all …]
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| /external/valgrind/main/VEX/ |
| D | TODO.txt | 8 And save FP and SSE insns across the helper.
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| /external/oprofile/events/i386/p4/ |
| D | events | 36 … um:flame_uop minimum:3000 name:SSE_INPUT_ASSIST : input assists requested for SSE or SSE2 operands
44 …um:x87_simd_moves_uop minimum:3000 name:X87_SIMD_MOVES_UOP : x87 FPU, MMX, SSE, or SSE2 loads, sto…
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