Searched refs:SSE2 (Results 1 – 25 of 68) sorted by relevance
123
1 …llc < %s -mattr=+sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE211 ; SSE2: t1:12 ; SSE2: movaps _.str, %xmm013 ; SSE2: movaps %xmm014 ; SSE2: movb $015 ; SSE2: movl $016 ; SSE2: movl $050 ; SSE2: t2:51 ; SSE2: movaps (%eax), %xmm052 ; SSE2: movaps %xmm0, (%eax)[all …]
1 ; RUN: llc < %s -march=x86 -mattr=-sse3,+sse2 | FileCheck %s -check-prefix=SSE212 ; SSE2: test1:13 ; SSE2-NOT: pcmpgtq14 ; SSE2: ret28 ; SSE2: test2:29 ; SSE2-NOT: pcmpeqq30 ; SSE2: ret
1 ; Tests for SSE1 and below, without SSE2+.
3 ; test vector shifts converted to proper SSE2 vector shifts when the shift
8 # gcc lameness is that, in order to compile SSE2 intrinsics code, it10 # emit SSE2 instructions even for scalar code, such as the CPUID11 # test used to test for the presence of SSE2. So that, and all other17 # SSE2, Linux x86_64 has SSE2 by definition, and MSC will happily emit18 # SSE2 from instrinsics, while generating plain ol' 386 for everything81 # to compile the SSE2 code with -mssse3 which would potentially allow
171 if (!CpuFeatures::IsSupported(SSE2)) return; in TEST()178 CHECK(CpuFeatures::IsSupported(SSE2)); in TEST()179 { CpuFeatures::Scope fscope(SSE2); in TEST()206 if (!CpuFeatures::IsSupported(SSE2)) return; in TEST()213 CHECK(CpuFeatures::IsSupported(SSE2)); in TEST()214 CpuFeatures::Scope fscope(SSE2); in TEST()263 if (!CpuFeatures::IsSupported(SSE2)) return; in TEST()266 CHECK(CpuFeatures::IsSupported(SSE2)); in TEST()267 CpuFeatures::Scope fscope(SSE2); in TEST()309 if (!CpuFeatures::IsSupported(SSE2)) return; in TEST()[all …]
351 if (CpuFeatures::IsSupported(SSE2)) { in TEST()352 CpuFeatures::Scope fscope(SSE2); in TEST()397 if (CpuFeatures::IsSupported(SSE2)) { in TEST()398 CpuFeatures::Scope fscope(SSE2); in TEST()
371 if (CpuFeatures::IsSupported(SSE2)) { in TEST()372 CpuFeatures::Scope fscope(SSE2); in TEST()416 if (CpuFeatures::IsSupported(SSE2)) { in TEST()417 CpuFeatures::Scope fscope(SSE2); in TEST()
409 if (!CpuFeatures::IsSupported(SSE2)) { in Nop()1922 ASSERT(CpuFeatures::IsEnabled(SSE2)); in cvttss2si()1932 ASSERT(CpuFeatures::IsEnabled(SSE2)); in cvttsd2si()1942 ASSERT(CpuFeatures::IsEnabled(SSE2)); in cvtsi2sd()1952 ASSERT(CpuFeatures::IsEnabled(SSE2)); in cvtss2sd()1962 ASSERT(CpuFeatures::IsEnabled(SSE2)); in cvtsd2ss()1972 ASSERT(CpuFeatures::IsEnabled(SSE2)); in addsd()1982 ASSERT(CpuFeatures::IsEnabled(SSE2)); in mulsd()1992 ASSERT(CpuFeatures::IsEnabled(SSE2)); in subsd()2002 ASSERT(CpuFeatures::IsEnabled(SSE2)); in divsd()[all …]
113 if (buffer == NULL || !CpuFeatures::IsSupported(SSE2)) return &sqrt; in CreateSqrtFunction()119 CpuFeatures::Scope use_sse2(SSE2); in CreateSqrtFunction()178 if (CpuFeatures::IsSupported(SSE2)) { in CreateMemCopyFunction()179 CpuFeatures::Scope enable(SSE2); in CreateMemCopyFunction()427 if (CpuFeatures::IsSupported(SSE2)) { in GenerateSmiOnlyToDouble()428 CpuFeatures::Scope use_sse2(SSE2); in GenerateSmiOnlyToDouble()452 if (CpuFeatures::IsSupported(SSE2)) { in GenerateSmiOnlyToDouble()453 CpuFeatures::Scope fscope(SSE2); in GenerateSmiOnlyToDouble()473 if (CpuFeatures::IsSupported(SSE2)) { in GenerateSmiOnlyToDouble()474 CpuFeatures::Scope use_sse2(SSE2); in GenerateSmiOnlyToDouble()[all …]
50 return CpuFeatures::IsSupported(SSE2); in SupportsCrankshaft()
525 CpuFeatures::Scope scope(SSE2); in Generate()542 CpuFeatures::Scope scope(SSE2); in Generate()1051 if (CpuFeatures::IsSupported(SSE2)) { in GenerateHeapNumberCodeBitNot()1052 CpuFeatures::Scope use_sse2(SSE2); in GenerateHeapNumberCodeBitNot()1490 if (CpuFeatures::IsSupported(SSE2)) { in GenerateSmiCode()1491 CpuFeatures::Scope use_sse2(SSE2); in GenerateSmiCode()1534 if (CpuFeatures::IsSupported(SSE2)) { in GenerateSmiCode()1535 CpuFeatures::Scope use_sse2(SSE2); in GenerateSmiCode()1696 if (CpuFeatures::IsSupported(SSE2)) { in GenerateInt32Stub()1697 CpuFeatures::Scope use_sse2(SSE2); in GenerateInt32Stub()[all …]
87 0x04 packed_double Retired Streaming SIMD Extensions 2 (SSE2) packed-double instructions88 0x08 scalar_double Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions89 0x10 vector Retired Streaming SIMD Extensions 2 (SSE2) vector instructions94 …0x04 packed_double Retired computational Streaming SIMD Extensions 2 (SSE2) packed-double instruct…95 …0x08 scalar_double Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instruct…
26 0x02 SSE2 Packed-Double27 0x03 SSE2 Scalar-Double
194 if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); } in AutoDetectSubtargetFeatures()390 if (X86SSELevel < SSE2) { in X86Subtarget()391 X86SSELevel = SSE2; in X86Subtarget()
44 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",45 "Enable SSE2 instructions",65 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied66 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2 enumerator194 bool hasSSE2() const { return X86SSELevel >= SSE2; } in hasSSE2()
364 // SSE2 Instruction Templates:366 // SDI - SSE2 instructions with XD prefix.367 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.368 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.369 // PDI - SSE2 instructions with TB and OpSize prefixes.370 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.371 // VSDI - SSE2 instructions with XD prefix in AVX form.372 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.592 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
36 … um:flame_uop minimum:3000 name:SSE_INPUT_ASSIST : input assists requested for SSE or SSE2 operands42 event:0x19 counters:2,6 um:flame_uop minimum:3000 name:128BIT_MMX_UOP : 128 bit integer SIMD SSE2 u…44 …md_moves_uop minimum:3000 name:X87_SIMD_MOVES_UOP : x87 FPU, MMX, SSE, or SSE2 loads, stores and r…
164 0x04 Retired SSE2 packed-double instructions165 0x08 Retired SSE2 scalar-double instructions166 0x10 Retired SSE2 vector integer instructions171 0x04 Retired computational SSE2 packed-double instructions172 0x08 Retired computational SSE2 scalar-double instructions
43 0x02 SSE2 Packed-Double44 0x03 SSE2 Scalar-Double
8 Specifically libyuv is optimized for SSE2/SSSE3 and Neon and has demonstrated
14 # Some SSE2 instructions start with 0xf2 or 0xf3