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Searched refs:SuperReg (Results 1 – 5 of 5) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonFrameLowering.cpp238 const uint16_t* SuperReg = TRI->getSuperRegisters(Reg); in spillCalleeSavedRegisters() local
241 assert(SuperReg[0] && !SuperReg[1] && "Expected exactly one superreg"); in spillCalleeSavedRegisters()
249 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]); in spillCalleeSavedRegisters()
250 CanUseDblStore = (SuperRegNext[0] == SuperReg[0]); in spillCalleeSavedRegisters()
255 TII.storeRegToStackSlot(MBB, MI, SuperReg[0], true, in spillCalleeSavedRegisters()
257 MBB.addLiveIn(SuperReg[0]); in spillCalleeSavedRegisters()
298 const uint16_t* SuperReg = TRI->getSuperRegisters(Reg); in restoreCalleeSavedRegisters() local
302 assert(SuperReg[0] && !SuperReg[1] && "Expected exactly one superreg"); in restoreCalleeSavedRegisters()
308 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]); in restoreCalleeSavedRegisters()
309 CanUseDblLoad = (SuperRegNext[0] == SuperReg[0]); in restoreCalleeSavedRegisters()
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/external/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp570 unsigned SuperReg = 0; in FindSuitableFreeRegisters() local
573 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) in FindSuitableFreeRegisters()
574 SuperReg = Reg; in FindSuitableFreeRegisters()
593 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
594 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
607 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) << in FindSuitableFreeRegisters()
621 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
644 if (NewSuperReg == SuperReg) continue; in FindSuitableFreeRegisters()
655 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
658 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
DCriticalAntiDepBreaker.cpp297 unsigned SuperReg = *Super; in ScanInstruction() local
298 Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1); in ScanInstruction()
DPostRASchedulerList.cpp466 const unsigned SuperReg = MO.getReg(); in ToggleKillFlag() local
467 for (const uint16_t *Subreg = TRI->getSubRegisters(SuperReg); in ToggleKillFlag()
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1718 SDValue SuperReg = SDValue(VLd, 0); in SelectVLD() local
1724 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
1950 SDValue SuperReg; in SelectVLDSTLane() local
1955 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
1957 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0); in SelectVLDSTLane()
1964 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
1966 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
1968 Ops.push_back(SuperReg); in SelectVLDSTLane()
1983 SuperReg = SDValue(VLdLn, 0); in SelectVLDSTLane()
1989 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
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