| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 29 namespace XCore { namespace
43 : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), in XCoreInstrInfo()
59 if (Opcode == XCore::LDWFI) in isLoadFromStackSlot()
81 if (Opcode == XCore::STWFI) in isStoreToStackSlot()
99 return BrOpc == XCore::BRFU_u6 in IsBRU()
100 || BrOpc == XCore::BRFU_lu6 in IsBRU()
101 || BrOpc == XCore::BRBU_u6 in IsBRU()
102 || BrOpc == XCore::BRBU_lu6; in IsBRU()
106 return BrOpc == XCore::BRFT_ru6 in IsBRT()
107 || BrOpc == XCore::BRFT_lru6 in IsBRT()
[all …]
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| D | XCoreRegisterInfo.cpp | 41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) { in XCoreRegisterInfo()
65 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
66 XCore::R8, XCore::R9, XCore::R10, XCore::LR, in getCalleeSavedRegs()
76 Reserved.set(XCore::CP); in getReservedRegs()
77 Reserved.set(XCore::DP); in getReservedRegs()
78 Reserved.set(XCore::SP); in getReservedRegs()
79 Reserved.set(XCore::LR); in getReservedRegs()
81 Reserved.set(XCore::R10); in getReservedRegs()
132 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) { in eliminateCallFramePseudoInstr()
133 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; in eliminateCallFramePseudoInstr()
[all …]
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| D | XCoreFrameLowering.cpp | 54 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in loadFromStack()
69 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in storeToStack()
106 loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII); in emitPrologue()
128 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6; in emitPrologue()
129 MBB.addLiveIn(XCore::LR); in emitPrologue()
133 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; in emitPrologue()
142 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel); in emitPrologue()
150 MachineLocation CSSrc(XCore::LR); in emitPrologue()
156 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII); in emitPrologue()
157 MBB.addLiveIn(XCore::LR); in emitPrologue()
[all …]
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| D | XCore.td | 1 //===-- XCore.td - Describe the XCore Target Machine -------*- tablegen -*-===//
10 // This is the top level entry point for the XCore target.
31 // XCore processors supported.
44 def XCore : Target {
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| D | XCoreISelDAGToDAG.cpp | 165 return CurDAG->getMachineNode(XCore::MKMSK_rus, dl, in Select()
173 SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, in Select()
187 return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32, in Select()
193 return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32, in Select()
199 return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32, in Select()
205 return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32, in Select()
211 return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32, in Select()
219 return CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32, MVT::i32, in Select()
290 SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue, in SelectBRIND()
293 SDValue(CurDAG->getMachineNode(XCore::CLRSR_branch_u6, dl, MVT::Glue, in SelectBRIND()
[all …]
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| D | LLVMBuild.txt | 1 ;===- ./lib/Target/XCore/LLVMBuild.txt -------------------------*- Conf -*--===;
23 name = XCore
30 parent = XCore
32 add_to_library_groups = XCore
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| D | XCoreRegisterInfo.td | 1 //===-- XCoreRegisterInfo.td - XCore Register defs ---------*- tablegen -*-===//
11 // Declarations that describe the XCore register file
16 let Namespace = "XCore";
45 def GRRegs : RegisterClass<"XCore", [i32], 32,
54 def RRegs : RegisterClass<"XCore", [i32], 32, (add CP, DP, SP, LR)> {
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| D | XCoreCallingConv.td | 1 //===- XCoreCallingConv.td - Calling Conventions for XCore -*- tablegen -*-===//
9 // This describes the calling conventions for XCore architecture.
13 // XCore Return Value Calling Convention
21 // XCore Argument Calling Conventions
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| D | XCoreInstrFormats.td | 1 //===-- XCoreInstrFormats.td - XCore Instruction Formats ---*- tablegen -*-===//
17 let Namespace = "XCore";
24 // XCore pseudo instructions format
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| D | Makefile | 12 TARGET = XCore
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| D | CMakeLists.txt | 1 set(LLVM_TARGET_DEFINITIONS XCore.td)
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| D | XCoreISelLowering.cpp | 69 addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass); in XCoreTargetLowering()
77 setStackPointerRegisterToSaveRestore(XCore::SP); in XCoreTargetLowering()
1125 XCore::GRRegsRegisterClass); in LowerCCCArguments()
1156 XCore::R0, XCore::R1, XCore::R2, XCore::R3 in LowerCCCArguments()
1176 XCore::GRRegsRegisterClass); in LowerCCCArguments()
1271 assert((MI->getOpcode() == XCore::SELECT_CC) && in EmitInstrWithCustomInserter()
1305 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6)) in EmitInstrWithCustomInserter()
1321 TII.get(XCore::PHI), MI->getOperand(0).getReg()) in EmitInstrWithCustomInserter()
1614 return std::make_pair(0U, XCore::GRRegsRegisterClass); in getRegForInlineAsmConstraint()
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| D | XCoreAsmPrinter.cpp | 299 case XCore::DBG_VALUE: { in EmitInstruction()
308 case XCore::ADD_2rus: in EmitInstruction()
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| D | XCoreInstrInfo.td | 1 //===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===//
10 // This file describes the XCore instructions in TableGen format.
26 // XCore specific DAG Nodes.
1230 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
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| /external/llvm/lib/Target/XCore/MCTargetDesc/ |
| D | LLVMBuild.txt | 1 ;===- ./lib/Target/XCore/MCTargetDesc/LLVMBuild.txt ------------*- Conf -*--===;
21 parent = XCore
23 add_to_library_groups = XCore
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| D | XCoreMCTargetDesc.cpp | 42 InitXCoreMCRegisterInfo(X, XCore::LR); in createXCoreMCRegisterInfo()
58 MachineLocation Src(XCore::SP, 0); in createXCoreMCAsmInfo()
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| /external/llvm/lib/Target/XCore/TargetInfo/ |
| D | LLVMBuild.txt | 1 ;===- ./lib/Target/XCore/TargetInfo/LLVMBuild.txt --------------*- Conf -*--===;
21 parent = XCore
23 add_to_library_groups = XCore
|
| /external/clang/utils/C++Tests/LLVM-Code-Syntax/ |
| D | lit.local.cfg | 28 '-I%s/lib/Target/XCore' % root.llvm_src_root,
39 '-I%s/lib/Target/XCore' % target_obj_root];
|
| /external/clang/utils/C++Tests/LLVM-Code-Compile/ |
| D | lit.local.cfg | 29 '-I%s/lib/Target/XCore' % root.llvm_src_root,
40 '-I%s/lib/Target/XCore' % target_obj_root];
|
| /external/clang/utils/C++Tests/LLVM-Code-Symbols/ |
| D | lit.local.cfg | 29 '-I%s/lib/Target/XCore' % root.llvm_src_root,
40 '-I%s/lib/Target/XCore' % target_obj_root];
|
| /external/llvm/test/CodeGen/XCore/ |
| D | lit.local.cfg | 4 if not 'XCore' in targets:
|
| /external/llvm/include/llvm/ |
| D | IntrinsicsXCore.td | 1 //==- IntrinsicsXCore.td - XCore intrinsics -*- tablegen -*-==//
10 // This file defines all of the XCore-specific intrinsics.
|
| /external/llvm/lib/Target/ |
| D | LLVMBuild.txt | 19 subdirectories = ARM CellSPU CppBackend Hexagon MBlaze MSP430 Mips PTX PowerPC Sparc X86 XCore
|
| /external/llvm/projects/sample/autoconf/ |
| D | configure.ac | 308 xcore-*) llvm_cv_target_arch="XCore" ;;
455 XCore) AC_SUBST(TARGET_HAS_JIT,0) ;;
576 …all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 Hexagon CppBackend MBlaze P…
586 xcore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
601 XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
|
| /external/llvm/autoconf/ |
| D | configure.ac | 368 xcore-*) llvm_cv_target_arch="XCore" ;;
515 XCore) AC_SUBST(TARGET_HAS_JIT,0) ;;
637 …all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CppBackend MBlaze PTX Hexag…
648 xcore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
663 XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
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