cycles (reference) in projects: external

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Searched refs:cycles (Results 1 – 25 of 178) sorted by relevance

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/external/llvm/lib/Target/ARM/
D	ARMScheduleA9.td	78 // No operand cycles 199 // FIXME: If address is 64-bit aligned, AGU cycles is 1. 339 // FIXME: If address is 64-bit aligned, AGU cycles is 1. 460 // Extra latency cycles since wbck is 2 cycles 469 // Extra latency cycles since wbck is 2 cycles 479 // Extra latency cycles since wbck is 4 cycles 488 // Extra latency cycles since wbck is 4 cycles 660 // Extra 1 latency cycle since wbck is 2 cycles 669 // Extra 1 latency cycle since wbck is 2 cycles 710 // FIXME: assumes 2 doubles which requires 2 LS cycles. [all …]
/external/llvm/lib/Target/MBlaze/
D	MBlazeSchedule3.td	25 [ 2 // result ready after two cycles 32 // pipeline stages except the execute stage, which takes three cycles. The 38 , InstrStage<3,[EX]>], // three cycles in execute stage 39 [ 4 // result ready after four cycles 45 // stages except the execute stage, which takes 34 cycles. The two 51 , InstrStage<34,[EX]>], // 34 cycles in execute stage 52 [ 35 // result ready after 35 cycles 59 // except the execute stage, which takes two cycles. The two source operands 65 , InstrStage<2,[EX]>], // two cycles in execute stage 66 [ 3 // result ready after three cycles [all …]
D	MBlazeSchedule5.td	27 [ 2 // result ready after two cycles 42 [ 2 // result ready after two cycles 48 // stages except the memory access stage, which takes 31 cycles. The two 55 , InstrStage<31,[MA]> // 31 cycles in memory access stage 57 [ 33 // result ready after 33 cycles 72 [ 3 // result ready after three cycles 109 [ 4 // result ready after four cycles 114 // except the memory access stage, which takes two cycles. The source 120 , InstrStage<2,[MA]> // two cycles in memory access stage 128 // cycles. The source operands are read during the decode stage and the [all …]
/external/antlr/antlr-3.4/tool/src/main/java/org/antlr/tool/
D	LeftRecursionCyclesMessage.java	`39 public Collection cycles; field in LeftRecursionCyclesMessage 41 public LeftRecursionCyclesMessage(Collection cycles) { in LeftRecursionCyclesMessage() argument 43 this.cycles = cycles; in LeftRecursionCyclesMessage() 48 st.add("listOfCycles", cycles); in toString()`
/external/oprofile/events/mips/rm7000/
D	events	4 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Clock cycles 13 event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles 25 …m:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache miss stall cycles (cycles where both cac… 27 …0x17 counters:0,1 um:zero minimum:500 name:FP_EXCEPTION_STALL_CYCLES : FP possible exception cycles 29 event:0x19 counters:0,1 um:zero minimum:500 name:COP0_SLIP_CYCLES : Coprocessor 0 slip cycles 30 event:0x1a counters:0,1 um:zero minimum:500 name:SLIP_CYCLES_PENDING_NON_BLKING_LOAD : Slip cycles … 31 …unters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Write buffer full stall cycles 32 …unters:0,1 um:zero minimum:500 name:CACHE_INSTRUCTION_STALL_CYCLES : Cache instruction stall cycles 33 event:0x1e counters:0,1 um:zero minimum:500 name:MULTIPLIER_STALL_CYCLES : Multiplier stall cycles 34 …,1 um:zero minimum:500 name:STALL_CYCLES_PENDING_NON_BLKING_LOAD : Stall cycles due to pending non…
/external/oprofile/events/mips/24K/
D	events	36 event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU 42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specif… 43 event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles 53 # Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events. 55 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an ins… 56 event:0x26 counters:0 um:zero minimum:500 name:SYNC_STALLS : 38-0 SYNC stall cycles 58 event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles 59 event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU stall cycles 60 event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2 stall cycles 61 event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM stall cycles [all …]
/external/oprofile/events/mips/rm9000/
D	events	4 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles 12 event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles 24 event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache-miss stall cycles 26 …,1 um:zero minimum:500 name:FP_POSSIBLE_EXCEPTION_CYCLES : Floating-point possible exception cycles 27 event:0x18 counters:0,1 um:zero minimum:500 name:MULTIPLIER_BUSY_SLIP_CYCLES : Slip cycles due to b… 28 event:0x19 counters:0,1 um:zero minimum:500 name:COP0_SLIP_CYCLES : Co-processor 0 slip cycles 29 event:0x1a counters:0,1 um:zero minimum:500 name:NONBLOCKING_LOAD_SLIP_CYCLES : Slip cycles due to … 30 event:0x1b counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Stall cycles due … 31 event:0x1c counters:0,1 um:zero minimum:500 name:CACHE_INSN_STALL_CYCLES : Stall cycles due to cach… 32 …minimum:500 name:NONBLOCKING_LOAD_PENDING_EXCEPTION_STALL_CYCLES : Stall cycles due to pending non…
/external/oprofile/events/mips/34K/
D	events	36 event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU 42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specif… 43 event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles 57 # Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events. 59 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an ins… 62 event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles 63 event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU stall cycles 64 event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2 stall cycles 65 event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM stall cycles 67 event:0x2d counters:0 um:zero minimum:500 name:LOAD_USE_STALLS : 45-0 Load to use stall cycles [all …]
/external/oprofile/events/mips/1004K/
D	events	36 event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU 42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specif… 43 event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles 55 …ro minimum:500 name:INTERVENTION_STALLS : 36-0 Cache coherence intervention processing stall cycles 58 # Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events. 60 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an ins… 63 event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles 64 event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU stall cycles 65 event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2 stall cycles 66 event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM stall cycles [all …]
/external/oprofile/events/avr32/
D	events	4 event:0x01 counters:1,2 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pi… 5 event:0x02 counters:1,2 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall due to data depen… 12 event:0x09 counters:1,2 um:zero minimum:500 name:CYCLES_DCACHE_WBUF_FULL : cycles stalled due to da… 14 event:0x0b counters:1,2 um:zero minimum:500 name:CYCLES_DCACHE_READ_MISS : cycles stalled due to da… 16 event:0x0d counters:1,2 um:zero minimum:500 name:CYCLES_WRITE_ACCESS : cycles when write access is … 18 event:0x0f counters:1,2 um:zero minimum:500 name:CYCLES_READ_ACCESS : cycles when read access is on… 20 event:0x11 counters:1,2 um:zero minimum:500 name:CYCLES_CACHE_STALL : cycles stalled doing read or … 22 event:0x13 counters:1,2 um:zero minimum:500 name:CYCLES_DCACHE_ACCESS : cycles when data cache acce… 27 event:0xff counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
/external/oprofile/events/ppc64/cell-be/
D	unit_masks	`10 0x000 Count cycles [mandatory] 12 0x001 Count cycles [mandatory] 22 0x001 Count cycles [mandatory] 32 0x001 Count cycles [mandatory] 45 0x001 Count cycles [default ] 51 0x001 Count cycles [mandatory] 64 0x001 Count cycles [default ] 70 0x001 Count cycles [mandatory] 76 0x0001 Count cycles [mandatory] 91 0x0001 Count cycles [default ] [all …]`
/external/oprofile/events/i386/ppro/
D	events	8 event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU … 12 event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is s… 13 event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is s… 23 event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy 24 event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer… 40 event:0x64 counters:0,1 um:zero minimum:500 name:BUS_DATA_RCV : bus cycles this processor is receiv… 41 event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : bus cycles this processor is driving… 42 event:0x7a counters:0,1 um:zero minimum:500 name:BUS_HIT_DRV : bus cycles this processor is driving… 43 event:0x7b counters:0,1 um:zero minimum:500 name:BUS_HITM_DRV : bus cycles this processor is drivin… 44 event:0x7e counters:0,1 um:zero minimum:500 name:BUS_SNOOP_STALL : cycles during bus snoop stall [all …]
/external/oprofile/events/arm/armv6/
D	events	4 event:0x01 counters:0,1 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pi… 5 event:0x02 counters:0,1 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to… 18 event:0x11 counters:0,1 um:zero minimum:500 name:LSU_STALL : cycles stalled because Load Store requ… 20 event:0x20 counters:0,1 um:zero minimum:500 name:ETMEXTOUT0 : nuber of cycles ETMEXTOUT[0] signal w… 21 event:0x21 counters:0,1 um:zero minimum:500 name:ETMEXTOUT1 : nuber of cycles ETMEXTOUT[1] signal w… 22 event:0x22 counters:0,1 um:zero minimum:500 name:ETMEXTOUT_BOTH : nuber of cycles both ETMEXTOUT [0… 23 event:0xff counters:0,1,2 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
/external/oprofile/events/arm/armv7-ca9/
D	events	12 event:0x60 counters:1,2,3,4,5,6 um:zero minimum:500 name:IC_DEP_STALL : Number of cycles where CPU … 13 event:0x61 counters:1,2,3,4,5,6 um:zero minimum:500 name:DC_DEP_STALL : Number of cycles where CPU … 17 event:0x66 counters:1,2,3,4,5,6 um:zero minimum:500 name:ISS_NO_DISP : Number of cycles where the i… 18 event:0x67 counters:1,2,3,4,5,6 um:zero minimum:500 name:ISS_EMPTY : Number of cycles where the iss… 29 event:0x80 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_PLD : Number of cycles where CPU is … 30 event:0x81 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_WRITE : Number of cycles where CPU i… 31 event:0x82 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_INS_TLB : Number of cycles where CPU… 32 event:0x83 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_DATA_TLB : Number of cycles where CP… 33 event:0x84 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_INS_UTLB : Number of cycles where CP… 34 event:0x85 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_DATA_ULTB : Number of cycles where C… [all …]
/external/oprofile/events/mips/74K/
D	events	21 event:0x3 counters:0,2 um:zero minimum:500 name:REDIRECT_STALLS : 3-0 Stall cycles due to register … 25 … counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss stall cycles 26 …s:0,2 um:zero minimum:500 name:UNCACHED_IFETCH_STALLS : 8-0 Uncached instruction fetch stall cycles 31 event:0xd counters:0,2 um:zero minimum:500 name:DDQ0_FULL_DR_STALLS : 13-0 DR stage stall cycles du… 32 event:0xe counters:0,2 um:zero minimum:500 name:ALCB_FULL_DR_STALLS : 14-0 DR stage stall cycles du… 33 event:0xf counters:0,2 um:zero minimum:500 name:CLDQ_FULL_DR_STALLS : 15-0 DR stage stall cycles du… 34 …m:zero minimum:500 name:ALU_EMPTY_CYCLES : 16-0 DDQ0 (ALU out-of-order dispatch queue) empty cycles 35 …_NOT_READY_CYCLES : 17-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instruc… 36 …_NO_ISSUES_CYCLES : 18-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instruc… 38 …-of-order dispatch queue) or DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles [all …]
/external/oprofile/events/i386/pii/
D	events	8 event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU … 12 event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is s… 13 event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is s… 23 event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy 24 event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer… 40 event:0x64 counters:0,1 um:zero minimum:500 name:BUS_DATA_RCV : bus cycles this processor is receiv… 41 event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : bus cycles this processor is driving… 42 event:0x7a counters:0,1 um:zero minimum:500 name:BUS_HIT_DRV : bus cycles this processor is driving… 43 event:0x7b counters:0,1 um:zero minimum:500 name:BUS_HITM_DRV : bus cycles this processor is drivin… 44 event:0x7e counters:0,1 um:zero minimum:500 name:BUS_SNOOP_STALL : cycles during bus snoop stall [all …]
/external/oprofile/events/i386/piii/
D	events	8 event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU … 12 event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is s… 13 event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is s… 23 event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy 24 event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer… 40 event:0x64 counters:0,1 um:zero minimum:500 name:BUS_DATA_RCV : bus cycles this processor is receiv… 41 event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : bus cycles this processor is driving… 42 event:0x7a counters:0,1 um:zero minimum:500 name:BUS_HIT_DRV : bus cycles this processor is driving… 43 event:0x7b counters:0,1 um:zero minimum:500 name:BUS_HITM_DRV : bus cycles this processor is drivin… 44 event:0x7e counters:0,1 um:zero minimum:500 name:BUS_SNOOP_STALL : cycles during bus snoop stall [all …]
/external/oprofile/events/ppc64/power5+/
D	events	21 …t:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles 24 …0X013 counters:3 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_utilization) Processor cycles 26 …t:0X015 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles 32 …:0X023 counters:3 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_completion) Processor cycles 34 …nt:0X025 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP2 : (Group 2 pm_completion) Run cycles 42 …X035 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP3 : (Group 3 pm_group_dispatch) Run cycles 50 event:0X045 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP4 : (Group 4 pm_clb1) Run cycles 58 event:0X055 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP5 : (Group 5 pm_clb2) Run cycles 66 …ent:0X065 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP6 : (Group 6 pm_gct_empty) Run cycles 74 …ent:0X075 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP7 : (Group 7 pm_gct_usage) Run cycles [all …]
/external/oprofile/events/ppc64/power5/
D	events	21 …t:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles 24 …0X013 counters:3 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_utilization) Processor cycles 26 …t:0X015 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles 32 …:0X023 counters:3 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_completion) Processor cycles 34 …nt:0X025 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP2 : (Group 2 pm_completion) Run cycles 42 …X035 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP3 : (Group 3 pm_group_dispatch) Run cycles 50 event:0X045 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP4 : (Group 4 pm_clb1) Run cycles 58 event:0X055 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP5 : (Group 5 pm_clb2) Run cycles 66 …ent:0X065 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP6 : (Group 6 pm_gct_empty) Run cycles 74 …ent:0X075 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP7 : (Group 7 pm_gct_usage) Run cycles [all …]
/external/oprofile/events/ppc64/970MP/
D	events	23 event:0X0010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_slice0) Run cycles 24 …ent:0X0011 counters:1 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles 28 …ent:0X0015 counters:5 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles 33 event:0X0020 counters:0 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles 34 event:0X0021 counters:1 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles 44 event:0X0031 counters:1 um:zero minimum:10000 name:PM_CYC_GRP3 : (Group 3 pm_basic) Processor cycles 55 event:0X0042 counters:2 um:zero minimum:10000 name:PM_CYC_GRP4 : (Group 4 pm_lsu) Processor cycles 67 event:0X0054 counters:4 um:zero minimum:10000 name:PM_CYC_GRP5 : (Group 5 pm_fpu1) Processor cycles 75 event:0X0062 counters:2 um:zero minimum:10000 name:PM_CYC_GRP6 : (Group 6 pm_fpu2) Processor cycles 90 …0X0077 counters:7 um:zero minimum:10000 name:PM_CYC_GRP7 : (Group 7 pm_isu_rename) Processor cycles [all …]
/external/oprofile/events/ppc64/970/
D	events	18 event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_slice0) Run cycles 19 event:0X011 counters:1 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles 23 event:0X015 counters:5 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles 28 event:0X020 counters:0 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles 29 event:0X021 counters:1 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles 39 event:0X031 counters:1 um:zero minimum:10000 name:PM_CYC_GRP3 : (Group 3 pm_basic) Processor cycles 50 event:0X042 counters:2 um:zero minimum:10000 name:PM_CYC_GRP4 : (Group 4 pm_lsu) Processor cycles 62 event:0X054 counters:4 um:zero minimum:10000 name:PM_CYC_GRP5 : (Group 5 pm_fpu1) Processor cycles 70 event:0X062 counters:2 um:zero minimum:10000 name:PM_CYC_GRP6 : (Group 6 pm_fpu2) Processor cycles 85 …:0X077 counters:7 um:zero minimum:10000 name:PM_CYC_GRP7 : (Group 7 pm_isu_rename) Processor cycles [all …]
/external/oprofile/events/i386/core/
D	events	5 event:0x3c counters:0,1 um:nonhlt minimum:6000 name:CPU_CLK_UNHALTED : Unhalted clock cycles 12 event:0x04 counters:0,1 um:zero minimum:500 name:SB_DRAINS : number of store buffer drain cycles 20 event:0x14 counters:0 um:zero minimum:1000 name:CYCLES_DIV_BUSY : cycles divider is busy 22 event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy 23 event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer… 43 event:0x48 counters:0,1 um:dc_pend_miss minimum:500 name:DCACHE_PEND_MISS : Weighted cycles of L1 m… 49 event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : External bus cycles this processor i… 50 event:0x62 counters:0,1 um:zero minimum:500 name:BUS_DRDY_CLOCKS : External bus cycles DRDY is asse… 51 event:0x63 counters:0,1 um:zero minimum:500 name:BUS_LOCK_CLOCKS : External bus cycles LOCK is asse… 52 event:0x64 counters:0,1 um:x40 minimum:500 name:BUS_DATA_RCV : External bus cycles this processor i… [all …]
/external/oprofile/events/i386/p6_mobile/
D	events	8 event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU … 12 event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is s… 13 event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is s… 23 event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy 24 event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer… 40 event:0x64 counters:0,1 um:zero minimum:500 name:BUS_DATA_RCV : bus cycles this processor is receiv… 41 event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : bus cycles this processor is driving… 42 event:0x7a counters:0,1 um:zero minimum:500 name:BUS_HIT_DRV : bus cycles this processor is driving… 43 event:0x7b counters:0,1 um:zero minimum:500 name:BUS_HITM_DRV : bus cycles this processor is drivin… 44 event:0x7e counters:0,1 um:zero minimum:500 name:BUS_SNOOP_STALL : cycles during bus snoop stall [all …]
/external/oprofile/events/i386/westmere/
D	unit_masks	62 0x01 ref_p Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter) 66 0x04 walk_cycles DTLB load miss page walk cycles 73 0x04 walk_cycles DTLB miss page walk cycles 95 0x01 lcp Length Change Prefix stall cycles 96 0x02 mru Stall cycles due to BPU MRU bypass 97 0x04 iq_full Instruction Queue full stall cycles 98 0x08 regen Regen stall cycles 99 0x0f any Any Instruction Length Decoder stall cycles 107 0x04 walk_cycles ITLB miss page walk cycles 128 0x04 cycles_stalled L1I instruction fetch stall cycles [all …]
/external/oprofile/events/ppc64/power4/
D	events	18 event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_slice0) Run cycles 19 event:0X011 counters:1 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles 23 event:0X015 counters:5 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles 28 event:0X020 counters:0 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles 29 event:0X021 counters:1 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles 39 event:0X031 counters:1 um:zero minimum:10000 name:PM_CYC_GRP3 : (Group 3 pm_basic) Processor cycles 53 event:0X045 counters:5 um:zero minimum:10000 name:PM_CYC_GRP4 : (Group 4 pm_ifu) Processor cycles 64 event:0X056 counters:6 um:zero minimum:10000 name:PM_CYC_GRP5 : (Group 5 pm_isu) Processor cycles 90 event:0X082 counters:2 um:zero minimum:10000 name:PM_CYC_GRP8 : (Group 8 pm_lsu) Processor cycles 105 event:0X097 counters:7 um:zero minimum:10000 name:PM_CYC_GRP9 : (Group 9 pm_xlate1) Processor cycles [all …]

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