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Searched refs:r3 (Results 1 – 25 of 416) sorted by relevance

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/external/valgrind/main/none/tests/arm/
Dv6intThumb.c518 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv); in old_main()
519 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv); in old_main()
520 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv); in old_main()
521 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv); in old_main()
522 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, cv); in old_main()
523 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv); in old_main()
524 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv); in old_main()
525 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv); in old_main()
526 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv); in old_main()
527 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv); in old_main()
[all …]
Dv6intARM.c425 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c); in main()
426 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c); in main()
427 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c); in main()
428 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c); in main()
429 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c); in main()
430 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c); in main()
431 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c); in main()
432 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c); in main()
433 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c); in main()
434 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c); in main()
[all …]
Dv6media.c170 TESTINST4("mla r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0); in main()
171 TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0); in main()
172 TESTINST4("mla r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0); in main()
173 TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0); in main()
174 TESTINST4("mla r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0); in main()
175 TESTINST4("mla r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0); in main()
179 TESTINST4("mlas r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0); in main()
180 TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0); in main()
181 TESTINST4("mlas r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0); in main()
182 TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0); in main()
[all …]
/external/openssl/crypto/sha/asm/
Dsha256-armv4.s30 sub r3,pc,#8 @ sha256_block_data_order
34 sub r14,r3,#256 @ K256
38 ldr r3,[r1],#4
40 ldrb r3,[r1,#3] @ 0
44 orr r3,r3,r12,lsl#8
45 orr r3,r3,r2,lsl#16
46 orr r3,r3,r0,lsl#24
53 add r3,r3,r1 @ from BODY_16_xx
55 rev r3,r3
62 str r3,[sp,#0*4]
[all …]
/external/llvm/test/MC/ARM/
Darm-arithmetic-aliases.s8 sub r2, r2, r3
9 sub r2, r3
13 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
14 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
18 add r2, r2, r3
19 add r2, r3
23 @ CHECK: add r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe0]
24 @ CHECK: add r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe0]
28 and r2, r2, r3
29 and r2, r3
[all …]
Dbasic-thumb-instructions.s47 adds r1, r2, r3
50 @ CHECK: adds r1, r2, r3 @ encoding: [0xd1,0x18]
77 add sp, r3
80 @ CHECK: add sp, r3 @ encoding: [0x9d,0x44]
97 asrs r2, r3, #32
98 asrs r2, r3, #5
99 asrs r2, r3, #1
102 asrs r3, r5, #21
104 @ CHECK: asrs r2, r3, #32 @ encoding: [0x1a,0x10]
105 @ CHECK: asrs r2, r3, #5 @ encoding: [0x5a,0x11]
[all …]
Dbasic-thumb2-instructions.s23 adc r3, r7, #0x00550055
26 adc r5, r3, #0x87000000
33 @ CHECK: adc r3, r7, #5570645 @ encoding: [0x47,0xf1,0x55,0x13]
36 @ CHECK: adc r5, r3, #2264924160 @ encoding: [0x43,0xf1,0x07,0x45]
45 adc.w r9, r1, r3
46 adcs.w r9, r1, r3
47 adc r0, r1, r3, ror #4
48 adcs r0, r1, r3, lsl #7
49 adc.w r0, r1, r3, lsr #31
50 adcs.w r0, r1, r3, asr #32
[all …]
Darm_instructions.s15 @ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
16 and r1,r2,r3
18 @ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
19 ands r1,r2,r3
21 @ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
22 eor r1,r2,r3
24 @ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
25 eors r1,r2,r3
27 @ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
28 sub r1,r2,r3
[all …]
Dbasic-arm-instructions.s130 adr r3, Lforward
138 @ CHECK: adr r3, Lforward @ encoding: [A,0x30'A',0x0f'A',0xe2'A']
156 add r4, r4, r3, asl r9
187 @ CHECK: add r4, r4, r3, lsl r9 @ encoding: [0x13,0x49,0x84,0xe0]
225 and r2, r3, #0x7fffffff
253 @ CHECK: bic r2, r3, #-2147483648 @ encoding: [0x02,0x21,0xc3,0xe3]
677 ldc2 p2, c6, [r3, #-224]
691 ldc p15, c7, [r3, #-120]!
704 ldccc p15, c7, [r3, #-120]!
718 @ CHECK: ldc2 p2, c6, [r3, #-224] @ encoding: [0x38,0x62,0x13,0xfd]
[all …]
Darm-aliases.s5 add r1, r2, r3, lsl #0
6 sub r1, r2, r3, ror #0
7 eor r1, r2, r3, lsr #0
8 orr r1, r2, r3, asr #0
9 and r1, r2, r3, ror #0
10 bic r1, r2, r3, lsl #0
12 @ CHECK: add r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0]
13 @ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
14 @ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
15 @ CHECK: orr r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1]
[all …]
/external/libvpx/vp8/common/ppc/
Dplatform_altivec.asm25 ;# r3 context_ptr
28 W v20, r3
29 W v21, r3
30 W v22, r3
31 W v23, r3
32 W v24, r3
33 W v25, r3
34 W v26, r3
35 W v27, r3
36 W v28, r3
[all …]
/external/libvpx/vp8/encoder/arm/armv6/
Dwalsh_v6.asm26 ldr r3, [r0, #4] ; [3 | 2]
34 qsubaddx r10, r2, r3 ; [c1|a1] [1-2 | 0+3]
35 qaddsubx r11, r2, r3 ; [b1|d1] [1+2 | 0-3]
40 qaddsubx r3, r11, r10 ; [0 | 3] [b1+a1 | d1-c1]
56 qadd16 r10, r3, r9 ; a1 [0+12 | 3+15]
59 qsub16 lr, r3, r9 ; d1 [0-12 | 3-15]
61 qadd16 r3, r10, r11 ; a2 [a1+b1] [0 | 3]
78 asrs r10, r3, #16
88 lsls r12, r3, #16
96 asrs r3, r4, #16
[all …]
/external/skia/src/core/asm/
Ds32a_d565_opaque.S43 andeq r3, r6, #63488 // 0xf800
45 orreq r3, r3, r2
46 orreq r3, r3, r6, lsr #27
47 streqh r3, [r0], #2 // *dst = r3; dst++
50 mov r3, r1, lsl #16
52 mov r5, r3, lsr #24
53 ldrh r3, [r0] // r3 = *dst
57 mov r1, r3, lsr #5
61 mov r1, r3, lsr #11
67 and r3, r3, #31 // 0x1f
[all …]
/external/libvpx/vp8/encoder/ppc/
Dvariance_altivec.asm75 load_aligned_16 v4, r3, r10
79 add r3, r3, r4
90 lwz r3, 12(r1)
96 stw r3, 0(r8) ;# sum
100 mullw r3, r3, r3 ;# sum*sum
101 srawi r3, r3, \DS ;# (sum*sum) >> DS
102 subf r3, r3, r4 ;# sse - ((sum*sum) >> DS)
108 load_aligned_16 v4, r3, r10
112 add r3, r3, r4
116 load_aligned_16 v6, r3, r10
[all …]
/external/llvm/test/MC/Disassembler/MBlaze/
Dmblaze_typea.txt7 # CHECK: add r1, r2, r3
10 # CHECK: addc r1, r2, r3
13 # CHECK: addk r1, r2, r3
16 # CHECK: addkc r1, r2, r3
19 # CHECK: and r1, r2, r3
22 # CHECK: andn r1, r2, r3
25 # CHECK: cmp r1, r2, r3
28 # CHECK: cmpu r1, r2, r3
31 # CHECK: idiv r1, r2, r3
34 # CHECK: idivu r1, r2, r3
[all …]
/external/valgrind/main/none/tests/s390x/
Dopcodes.h22 #define RIE_RRI0(op1,r1,r3,i2,u0,op2) \ argument
23 ".short 0x" #op1 #r1 #r3 "\n\t" \
25 #define RRF_R0RR2(op,r3,u0,r1,r2) ".long 0x" #op #r3 #u0 #r1 #r2 "\n\t" argument
66 #define RSY_RURD(op1,r1,r3,b2,dl2,dh2,op2) \ argument
67 ".short 0x" #op1 #r1 #r3 "\n\t" \
69 #define RRF_F0FF2(op,r3,u0,r1,r2) ".long 0x" #op #r3 #u0 #r1 #r2 "\n\t" argument
70 #define RSY_RRRD(op1,r1,r3,b2,dl2,dh2,op2) \ argument
71 ".short 0x" #op1 #r1 #r3 "\n\t" \
73 #define RSY_AARD(op1,r1,r3,b2,dl2,dh2,op2) \ argument
74 ".short 0x" #op1 #r1 #r3 "\n\t" \
[all …]
/external/llvm/test/MC/MBlaze/
Dmblaze_typea.s12 add r1, r2, r3
17 addc r1, r2, r3
22 addk r1, r2, r3
27 addkc r1, r2, r3
32 and r1, r2, r3
37 andn r1, r2, r3
42 cmp r1, r2, r3
47 cmpu r1, r2, r3
52 idiv r1, r2, r3
57 idivu r1, r2, r3
[all …]
/external/tremolo/Tremolo/
DbitwiseARM.s46 LDMIA r0,{r2,r3,r12}
48 @ r3 = ptr
53 LDR r10,[r3] @ r10= ptr[0]
56 LDRLT r11,[r3,#4]! @ r11= ptr[1]
78 LDR r10,[r3],#4 @ r10= ptr[0]
79 LDRLT r6,[r3] @ r6 = ptr[1]
162 LDMIA r0,{r2,r3,r12}
164 @ r3 = ptr
170 ADDLE r3,r3,#4
171 STMIA r0,{r2,r3,r12}
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dthumb1.txt25 # CHECK: adds r1, r2, r3
48 # CHECK: add sp, r3
63 # CHECK: asrs r2, r3, #32
64 # CHECK: asrs r2, r3, #5
65 # CHECK: asrs r2, r3, #1
119 # CHECK: cmp r3, r4
136 # CHECK: ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}
137 # CHECK: ldm r2!, {r1, r3, r4, r5, r7}
150 # CHECK: ldr r3, [r7, #124]
153 # CHECK: ldr r3, [sp, #1020]
[all …]
/external/qemu/distrib/jpeg-6b/
Darmv6_idct.S84 stm r5, {r2, r3, r4}
95 ldrsh r3, [r14, #48]
107 orreqs r8, r3, r5
135 mla r3, r11, r3, r5
148 sub r1, r1, r3
149 rsb r5, r3, r5, lsl #1
150 add r3, r1, r3, lsl #1
176 add r0, r0, r3
185 rsb r7, r3, r5, lsl #3
186 sub r3, r0, r3, lsl #1
[all …]
/external/jpeg/
Darmv6_idct.S84 stm r5, {r2, r3, r4}
95 ldrsh r3, [r14, #48]
107 orreqs r8, r3, r5
135 mla r3, r11, r3, r5
148 sub r1, r1, r3
149 rsb r5, r3, r5, lsl #1
150 add r3, r1, r3, lsl #1
176 add r0, r0, r3
185 rsb r7, r3, r5, lsl #3
186 sub r3, r0, r3, lsl #1
[all …]
/external/libffi/src/powerpc/
Daix_closure.S30 .set r3,3 define
120 stw r3, 200(r1)
146 mr r3,r11
169 slwi r3,r3,2 /* now multiply return type by 4 */
170 lwzx r3,r4,r3 /* get the contents of that table value */
171 add r3,r3,r4 /* add contents of table to table address */
172 mtctr r3
205 lwz r3,0(r5)
211 lwz r3,0(r5)
217 lbz r3,0(r5)
[all …]
Dppc_closure.S48 stw %r3, 16(%r1)
71 mr %r3,%r11
90 # now r3 contains the return type
98 slwi %r3,%r3,4 # now multiply return type by 16
101 add %r3,%r3,%r4 # add contents of table to table address
102 mtctr %r3
118 lwz %r3,112+0(%r1)
143 lbz %r3,112+3(%r1)
149 lbz %r3,112+3(%r1)
150 extsb %r3,%r3
[all …]
/external/libvpx/vp8/encoder/arm/neon/
Dsad8_neon.asm29 vld1.8 {d8}, [r2], r3
32 vld1.8 {d10}, [r2], r3
37 vld1.8 {d12}, [r2], r3
42 vld1.8 {d14}, [r2], r3
47 vld1.8 {d8}, [r2], r3
52 vld1.8 {d10}, [r2], r3
57 vld1.8 {d12}, [r2], r3
62 vld1.8 {d14}, [r2], r3
86 vld1.8 {d8}, [r2], r3
89 vld1.8 {d10}, [r2], r3
[all …]
/external/skia/src/opts/
Dmemset.arm.S74 rsb r3, r0, #0
75 ands r3, r3, #0x1C
77 cmp r3, r2
78 andhi r3, r2, #0x1C
79 sub r2, r2, r3
83 movs r3, r3, lsl #28
87 movs r3, r3, lsl #2
92 mov r3, r1
94 stmhsia r0!, {r1,r3,ip,lr}
95 stmhsia r0!, {r1,r3,ip,lr}
[all …]

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