| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeInstrFPU.td | 140 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETEQ),
143 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETNE),
146 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOEQ),
149 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
153 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
157 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGT),
160 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLT),
163 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGE),
166 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLE),
169 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGT),
[all …]
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| D | MBlazeInstrInfo.td | 763 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETEQ),
765 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETNE),
767 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETGT),
769 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETLT),
771 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETGE),
773 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETLE),
775 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETUGT),
778 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETULT),
781 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETUGE),
784 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETULE),
[all …]
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| /external/llvm/lib/Target/PTX/ |
| D | PTXInstrInfo.td | 282 [(set RegPred:$p, (setcc RC:$a, RC:$b, cmp))]>;
286 [(set RegPred:$p, (setcc RC:$a, imm:$b, cmp))]>;
292 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
297 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp),
303 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
308 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
313 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
318 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp),
325 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp),
331 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp),
[all …]
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 144 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
397 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
815 // setcc convenience fragments.
817 (setcc node:$lhs, node:$rhs, SETOEQ)>;
819 (setcc node:$lhs, node:$rhs, SETOGT)>;
821 (setcc node:$lhs, node:$rhs, SETOGE)>;
823 (setcc node:$lhs, node:$rhs, SETOLT)>;
825 (setcc node:$lhs, node:$rhs, SETOLE)>;
827 (setcc node:$lhs, node:$rhs, SETONE)>;
829 (setcc node:$lhs, node:$rhs, SETO)>;
[all …]
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| /external/llvm/test/Transforms/LoopStrengthReduce/ |
| D | exit_compare_live_range.ll | 2 ; having overlapping live ranges that result in copies. We want the setcc
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPU64InstrInfo.td | 18 // 3. i64 setcc results are i32, which are subsequently converted to a FSM
21 // 4. v2i64 setcc results are v4i32, which can be converted to a FSM mask (TODO)
48 // setcc the negative condition:
64 // i64 seteq (equality): the setcc result is i32, which is converted to a
67 // v2i64 seteq (equality): the setcc result is v4i32
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| D | SPUInstrInfo.td | 3225 // 1. This only matches the setcc set of conditionals. Special pattern
3588 // setcc and brcond patterns:
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| /external/llvm/test/CodeGen/X86/ |
| D | cmov.ll | 118 ; Should compile to setcc | -2.
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 265 // setcc patterns
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| D | MipsInstrInfo.td | 1140 // setcc patterns
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 1163 /// setcc patterns, only matched when none of the above brcond
1167 // setcc 2 register operands
1194 // setcc reg/imm operands
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| /external/v8/src/ia32/ |
| D | assembler-ia32.h | 971 void setcc(Condition cc, Register reg);
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| D | assembler-ia32.cc | 1912 void Assembler::setcc(Condition cc, Register reg) { in setcc() function in v8::internal::Assembler
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| D | macro-assembler-ia32.cc | 152 setcc(negative, reg); // 1 if negative, 0 if positive. in ClampUint8()
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| D | code-stubs-ia32.cc | 4312 __ setcc(above_equal, eax); in Generate() local
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| /external/llvm/lib/Target/X86/ |
| D | README.txt | 259 are a number of issues. 1) We are introducing a setcc between the result of the
648 The X86 backend should fold (branch (or (setcc, setcc))) into multiple
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| /external/v8/src/x64/ |
| D | assembler-x64.h | 1179 void setcc(Condition cc, Register reg);
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| D | code-stubs-x64.cc | 3370 __ setcc(parity_even, rax); in Generate() local
3451 __ setcc(above, rax); in Generate() local
3452 __ setcc(below, rcx); in Generate() local
5554 __ setcc(above, rax); // Add one to zero if carry clear and not equal. in GenerateHeapNumbers() local
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| D | assembler-x64.cc | 1929 void Assembler::setcc(Condition cc, Register reg) { in setcc() function in v8::internal::Assembler
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| D | stub-cache-x64.cc | 3306 __ setcc(negative, rdx); // 1 if negative, 0 if positive. in GenerateStoreExternalArray() local
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| D | macro-assembler-x64.cc | 2781 setcc(negative, reg); // 1 if negative, 0 if positive. in ClampUint8()
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| /external/llvm/lib/Target/PowerPC/ |
| D | README.txt | 333 We should custom expand setcc instead of pretending that we have it. That
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.td | 2682 // Map brcond with an unsupported setcc to a JMP_cNot.
|