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Searched refs:subopc (Results 1 – 7 of 7) sorted by relevance

/external/valgrind/main/VEX/priv/
Dhost_arm_defs.c2719 UInt instr, subopc; in emit_ARMInstr() local
2725 case ARMalu_ADD: subopc = X0100; break; in emit_ARMInstr()
2726 case ARMalu_ADC: subopc = X0101; break; in emit_ARMInstr()
2728 case ARMalu_SUB: subopc = X0010; break; in emit_ARMInstr()
2729 case ARMalu_SBC: subopc = X0110; break; in emit_ARMInstr()
2730 case ARMalu_AND: subopc = X0000; break; in emit_ARMInstr()
2731 case ARMalu_BIC: subopc = X1110; break; in emit_ARMInstr()
2732 case ARMalu_OR: subopc = X1100; break; in emit_ARMInstr()
2733 case ARMalu_XOR: subopc = X0001; break; in emit_ARMInstr()
2737 instr |= XXXXX___(X1110, (1 & (subopc >> 3)), in emit_ARMInstr()
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Dhost_x86_defs.c1943 Int subopc; in do_fop2_st() local
1945 case Xfp_ADD: subopc = 0; break; in do_fop2_st()
1946 case Xfp_SUB: subopc = 4; break; in do_fop2_st()
1947 case Xfp_MUL: subopc = 1; break; in do_fop2_st()
1948 case Xfp_DIV: subopc = 6; break; in do_fop2_st()
1952 p = doAMode_R(p, fake(subopc), fake(i)); in do_fop2_st()
1996 UInt irno, opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; in emit_X86Instr() local
2169 opc_cl = opc_imm = subopc = 0; in emit_X86Instr()
2171 case Xsh_SHR: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 5; break; in emit_X86Instr()
2172 case Xsh_SAR: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 7; break; in emit_X86Instr()
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Dhost_amd64_defs.c2351 UInt /*irno,*/ opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; in emit_AMD64Instr() local
2580 opc_cl = opc_imm = subopc = 0; in emit_AMD64Instr()
2582 case Ash_SHR: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 5; break; in emit_AMD64Instr()
2583 case Ash_SAR: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 7; break; in emit_AMD64Instr()
2584 case Ash_SHL: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 4; break; in emit_AMD64Instr()
2590 p = doAMode_R(p, fake(subopc), i->Ain.Sh64.dst); in emit_AMD64Instr()
2595 p = doAMode_R(p, fake(subopc), i->Ain.Sh64.dst); in emit_AMD64Instr()
2694 subopc = i->Ain.MulL.syned ? 5 : 4; in emit_AMD64Instr()
2700 p = doAMode_M(p, fake(subopc), in emit_AMD64Instr()
2707 p = doAMode_R(p, fake(subopc), in emit_AMD64Instr()
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Dguest_x86_toIR.c5954 UChar byte2, subopc; in dis_MMX() local
5958 subopc = toUChar( (byte2 >> 3) & 7 ); in dis_MMX()
5964 if (subopc == 2 /*SRL*/ && opc == 0x71) in dis_MMX()
5966 else if (subopc == 2 /*SRL*/ && opc == 0x72) in dis_MMX()
5968 else if (subopc == 2 /*SRL*/ && opc == 0x73) in dis_MMX()
5971 else if (subopc == 4 /*SAR*/ && opc == 0x71) in dis_MMX()
5973 else if (subopc == 4 /*SAR*/ && opc == 0x72) in dis_MMX()
5976 else if (subopc == 6 /*SHL*/ && opc == 0x71) in dis_MMX()
5978 else if (subopc == 6 /*SHL*/ && opc == 0x72) in dis_MMX()
5980 else if (subopc == 6 /*SHL*/ && opc == 0x73) in dis_MMX()
Dguest_amd64_toIR.c7094 UChar byte2, subopc; in dis_MMX() local
7098 subopc = toUChar( (byte2 >> 3) & 7 ); in dis_MMX()
7104 if (subopc == 2 /*SRL*/ && opc == 0x71) in dis_MMX()
7106 else if (subopc == 2 /*SRL*/ && opc == 0x72) in dis_MMX()
7108 else if (subopc == 2 /*SRL*/ && opc == 0x73) in dis_MMX()
7111 else if (subopc == 4 /*SAR*/ && opc == 0x71) in dis_MMX()
7113 else if (subopc == 4 /*SAR*/ && opc == 0x72) in dis_MMX()
7116 else if (subopc == 6 /*SHL*/ && opc == 0x71) in dis_MMX()
7118 else if (subopc == 6 /*SHL*/ && opc == 0x72) in dis_MMX()
7120 else if (subopc == 6 /*SHL*/ && opc == 0x73) in dis_MMX()
Dguest_arm_toIR.c13587 UInt subopc = INSN(27,20) & BITS8(0,0,0,0,0, 1,1,1); in disInstr_ARM_WRK() local
13588 if (subopc != BITS4(0,0,0,1) && subopc != BITS4(0,1,0,1)) { in disInstr_ARM_WRK()
13598 switch (subopc) { in disInstr_ARM_WRK()
/external/qemu/tcg/i386/
Dtcg-target.c579 static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count) in tcg_out_shifti() argument
582 int ext = subopc & ~0x7; in tcg_out_shifti()
583 subopc &= 0x7; in tcg_out_shifti()
586 tcg_out_modrm(s, OPC_SHIFT_1 + ext, subopc, reg); in tcg_out_shifti()
588 tcg_out_modrm(s, OPC_SHIFT_Ib + ext, subopc, reg); in tcg_out_shifti()