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/external/llvm/test/CodeGen/X86/
Dvec_splat-4.ll11 …%tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 0, i32 undef, i32 undef, i3…
12 ret <16 x i8 > %tmp6
17 …%tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 1, i32 1, i32 undef, i32 un…
18 ret <16 x i8 > %tmp6
23 …%tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 2, i32 undef, i32 undef, i3…
24 ret <16 x i8 > %tmp6
29 …%tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 3, i32 undef, i32 undef, i3…
30 ret <16 x i8 > %tmp6
36 …%tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 4, i32 undef, i32 undef, i3…
37 ret <16 x i8 > %tmp6
[all …]
Dvec_splat-3.ll10 …%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 0, i32 undef, i32 undef, i32 0…
11 ret <8 x i16> %tmp6
16 …%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 1, i32 1, i32 undef, i32 undef…
17 ret <8 x i16> %tmp6
22 …%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 2, i32 undef, i32 undef, i32 2…
23 ret <8 x i16> %tmp6
28 …%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 3, i32 3, i32 undef, i32 undef…
29 ret <8 x i16> %tmp6
34 …%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 4, i32 undef, i32 undef, i32 u…
35 ret <8 x i16> %tmp6
[all …]
Dvec_shuffle-14.ll10 …%tmp6 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp, <4 x i32> < i32 4, i32 1, i32 2, …
11 ret <4 x i32> %tmp6
17 …%tmp6 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %tmp, <2 x i32> < i32 2, i32 1 > ; <<4…
18 ret <2 x i64> %tmp6
24 %tmp6 = bitcast <2 x i64> %tmp4 to <4 x i32> ; <<4 x i32>> [#uses=1]
25 …%tmp7 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp6, <4 x i32> < i32 4, i32 5, i32 2,…
33 …%tmp6 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp5, <4 x i32> < i32 4, i32 5, i32 2,…
34 %tmp7 = bitcast <4 x i32> %tmp6 to <2 x i64> ; <<2 x i64>> [#uses=1]
40 …%tmp6 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %a, <2 x i32> < i32 2, i32 1 > ; <<4 x…
41 ret <2 x i64> %tmp6
/external/llvm/test/CodeGen/ARM/
Ddyn-stackalloc.ll10 %tmp6 = load i32* null
11 %tmp8 = alloca float, i32 %tmp6
38 %tmp6 = alloca i8, i32 %tmp5
39 %tmp9 = call i8* @strcpy(i8* %tmp6, i8* %tag)
40 %tmp6.len = call i32 @strlen(i8* %tmp6)
41 %tmp6.indexed = getelementptr i8* %tmp6, i32 %tmp6.len
42 …call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp6.indexed, i8* getelementptr inbounds ([2 x i8]* @str…
43 %tmp15 = call i8* @strcat(i8* %tmp6, i8* %contents)
44 call fastcc void @comment_add(%struct.comment* %vc, i8* %tmp6)
Dvbsl.ll11 %tmp6 = and <8 x i8> %tmp5, %tmp3
12 %tmp7 = or <8 x i8> %tmp4, %tmp6
24 %tmp6 = and <4 x i16> %tmp5, %tmp3
25 %tmp7 = or <4 x i16> %tmp4, %tmp6
37 %tmp6 = and <2 x i32> %tmp5, %tmp3
38 %tmp7 = or <2 x i32> %tmp4, %tmp6
50 %tmp6 = and <1 x i64> %tmp5, %tmp3
51 %tmp7 = or <1 x i64> %tmp4, %tmp6
63 %tmp6 = and <16 x i8> %tmp5, %tmp3
64 %tmp7 = or <16 x i8> %tmp4, %tmp6
[all …]
Dvbsl-constant.ll12 %tmp6 = and <8 x i8> %tmp3, <i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4>
13 %tmp7 = or <8 x i8> %tmp4, %tmp6
26 %tmp6 = and <4 x i16> %tmp3, <i16 -4, i16 -4, i16 -4, i16 -4>
27 %tmp7 = or <4 x i16> %tmp4, %tmp6
40 %tmp6 = and <2 x i32> %tmp3, <i32 -4, i32 -4>
41 %tmp7 = or <2 x i32> %tmp4, %tmp6
55 %tmp6 = and <1 x i64> %tmp3, <i64 -4>
56 %tmp7 = or <1 x i64> %tmp4, %tmp6
69 …%tmp6 = and <16 x i8> %tmp3, <i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4…
70 %tmp7 = or <16 x i8> %tmp4, %tmp6
[all …]
Duxtb.ll23 %tmp6 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
24 ret i32 %tmp6
38 %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
39 ret i32 %tmp6
47 %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
48 ret i32 %tmp6
55 %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
56 ret i32 %tmp6
63 %tmp6 = or i32 %tmp5, %tmp1 ; <i32> [#uses=1]
64 ret i32 %tmp6
/external/llvm/test/CodeGen/Thumb/
Ddyn-stackalloc.ll15 %tmp6 = load i32* null
16 %tmp8 = alloca float, i32 %tmp6
59 %tmp6 = alloca i8, i32 %tmp5
60 %tmp9 = call i8* @strcpy( i8* %tmp6, i8* %tag )
61 %tmp6.len = call i32 @strlen( i8* %tmp6 )
62 %tmp6.indexed = getelementptr i8* %tmp6, i32 %tmp6.len
63 …call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp6.indexed, i8* getelementptr inbounds ([2 x i8]* @str…
64 %tmp15 = call i8* @strcat( i8* %tmp6, i8* %contents )
65 call fastcc void @comment_add( %struct.comment* %vc, i8* %tmp6 )
/external/jpeg/
Djfdctint.c142 INT32 tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
158 tmp6 = dataptr[1] - dataptr[6];
188 z2 = tmp5 + tmp6;
189 z3 = tmp4 + tmp6;
195 tmp6 = MULTIPLY(tmp6, FIX_3_072711026); /* sqrt(2) * ( c1+c3+c5-c7) */
207 dataptr[3] = (DCTELEM) DESCALE(tmp6 + z2 + z3, CONST_BITS-PASS1_BITS);
223 tmp6 = dataptr[DCTSIZE*1] - dataptr[DCTSIZE*6];
253 z2 = tmp5 + tmp6;
254 z3 = tmp4 + tmp6;
260 tmp6 = MULTIPLY(tmp6, FIX_3_072711026); /* sqrt(2) * ( c1+c3+c5-c7) */
[all …]
Djidctflt.c72 FAST_FLOAT tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
143 tmp6 = DEQUANTIZE(inptr[DCTSIZE*5], quantptr[DCTSIZE*5]);
146 z13 = tmp6 + tmp5; /* phase 6 */
147 z10 = tmp6 - tmp5;
158 tmp6 = tmp12 - tmp7; /* phase 2 */
159 tmp5 = tmp11 - tmp6;
164 wsptr[DCTSIZE*1] = tmp1 + tmp6;
165 wsptr[DCTSIZE*6] = tmp1 - tmp6;
215 tmp6 = tmp12 - tmp7;
216 tmp5 = tmp11 - tmp6;
[all …]
Djidctfst.c172 DCTELEM tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
244 tmp6 = DEQUANTIZE(inptr[DCTSIZE*5], quantptr[DCTSIZE*5]);
247 z13 = tmp6 + tmp5; /* phase 6 */
248 z10 = tmp6 - tmp5;
259 tmp6 = tmp12 - tmp7; /* phase 2 */
260 tmp5 = tmp11 - tmp6;
265 wsptr[DCTSIZE*1] = (int) (tmp1 + tmp6);
266 wsptr[DCTSIZE*6] = (int) (tmp1 - tmp6);
341 tmp6 = tmp12 - tmp7; /* phase 2 */
342 tmp5 = tmp11 - tmp6;
[all …]
Djfdctflt.c61 FAST_FLOAT tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
74 tmp6 = dataptr[1] - dataptr[6];
97 tmp11 = tmp5 + tmp6;
98 tmp12 = tmp6 + tmp7;
124 tmp6 = dataptr[DCTSIZE*1] - dataptr[DCTSIZE*6];
147 tmp11 = tmp5 + tmp6;
148 tmp12 = tmp6 + tmp7;
Djfdctfst.c116 DCTELEM tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
130 tmp6 = dataptr[1] - dataptr[6];
153 tmp11 = tmp5 + tmp6;
154 tmp12 = tmp6 + tmp7;
180 tmp6 = dataptr[DCTSIZE*1] - dataptr[DCTSIZE*6];
203 tmp11 = tmp5 + tmp6;
204 tmp12 = tmp6 + tmp7;
/external/qemu/distrib/jpeg-6b/
Djfdctint.c142 INT32 tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
158 tmp6 = dataptr[1] - dataptr[6];
188 z2 = tmp5 + tmp6;
189 z3 = tmp4 + tmp6;
195 tmp6 = MULTIPLY(tmp6, FIX_3_072711026); /* sqrt(2) * ( c1+c3+c5-c7) */
207 dataptr[3] = (DCTELEM) DESCALE(tmp6 + z2 + z3, CONST_BITS-PASS1_BITS);
223 tmp6 = dataptr[DCTSIZE*1] - dataptr[DCTSIZE*6];
253 z2 = tmp5 + tmp6;
254 z3 = tmp4 + tmp6;
260 tmp6 = MULTIPLY(tmp6, FIX_3_072711026); /* sqrt(2) * ( c1+c3+c5-c7) */
[all …]
Djidctflt.c72 FAST_FLOAT tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
143 tmp6 = DEQUANTIZE(inptr[DCTSIZE*5], quantptr[DCTSIZE*5]);
146 z13 = tmp6 + tmp5; /* phase 6 */
147 z10 = tmp6 - tmp5;
158 tmp6 = tmp12 - tmp7; /* phase 2 */
159 tmp5 = tmp11 - tmp6;
164 wsptr[DCTSIZE*1] = tmp1 + tmp6;
165 wsptr[DCTSIZE*6] = tmp1 - tmp6;
215 tmp6 = tmp12 - tmp7;
216 tmp5 = tmp11 - tmp6;
[all …]
Djidctfst.c172 DCTELEM tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
244 tmp6 = DEQUANTIZE(inptr[DCTSIZE*5], quantptr[DCTSIZE*5]);
247 z13 = tmp6 + tmp5; /* phase 6 */
248 z10 = tmp6 - tmp5;
259 tmp6 = tmp12 - tmp7; /* phase 2 */
260 tmp5 = tmp11 - tmp6;
265 wsptr[DCTSIZE*1] = (int) (tmp1 + tmp6);
266 wsptr[DCTSIZE*6] = (int) (tmp1 - tmp6);
341 tmp6 = tmp12 - tmp7; /* phase 2 */
342 tmp5 = tmp11 - tmp6;
[all …]
Djfdctflt.c61 FAST_FLOAT tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
74 tmp6 = dataptr[1] - dataptr[6];
97 tmp11 = tmp5 + tmp6;
98 tmp12 = tmp6 + tmp7;
124 tmp6 = dataptr[DCTSIZE*1] - dataptr[DCTSIZE*6];
147 tmp11 = tmp5 + tmp6;
148 tmp12 = tmp6 + tmp7;
Djfdctfst.c116 DCTELEM tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
130 tmp6 = dataptr[1] - dataptr[6];
153 tmp11 = tmp5 + tmp6;
154 tmp12 = tmp6 + tmp7;
180 tmp6 = dataptr[DCTSIZE*1] - dataptr[DCTSIZE*6];
203 tmp11 = tmp5 + tmp6;
204 tmp12 = tmp6 + tmp7;
/external/llvm/test/CodeGen/PowerPC/
D2006-01-20-ShiftPartsCrash.ll9 %tmp6.u = add i32 %tmp5, 32 ; <i32> [#uses=1]
10 %tmp6 = bitcast i32 %tmp6.u to i32 ; <i32> [#uses=1]
12 %tmp6.upgrd.1 = trunc i32 %tmp6 to i8 ; <i8> [#uses=1]
13 %shift.upgrd.2 = zext i8 %tmp6.upgrd.1 to i64 ; <i64> [#uses=1]
/external/llvm/test/Transforms/InstCombine/
Dand-or-not.ll13 %tmp6 = and i32 %b, %a ; <i32> [#uses=1]
14 %tmp7 = or i32 %tmp6, %tmp3not ; <i32> [#uses=1]
22 %tmp6 = and i32 %b, %a ; <i32> [#uses=1]
23 %tmp6not = xor i32 %tmp6, -1 ; <i32> [#uses=1]
32 %tmp6 = and <4 x i32> %a, %b ; <<4 x i32>> [#uses=1]
33 %tmp7 = or <4 x i32> %tmp6, %tmp3not ; <<4 x i32>> [#uses=1]
41 %tmp6 = and <4 x i32> %a, %b ; <<4 x i32>> [#uses=1]
42 …%tmp6not = xor <4 x i32> %tmp6, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#us…
Dvec_shuffle.ll79 define <4 x i8> @test9(<16 x i8> %tmp6) nounwind {
83 …%tmp7 = shufflevector <16 x i8> %tmp6, <16 x i8> undef, <4 x i32> < i32 13, i32 9, i32 4, i32 13 >…
91 define <4 x i8> @test9a(<16 x i8> %tmp6) nounwind {
96 …%tmp7 = shufflevector <16 x i8> %tmp6, <16 x i8> undef, <4 x i32> < i32 undef, i32 9, i32 4, i32 8…
103 define <4 x i8> @test9b(<4 x i8> %tmp6, <4 x i8> %tmp7) nounwind {
107 …%tmp1 = shufflevector <4 x i8> %tmp6, <4 x i8> %tmp7, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 4…
117 …%tmp6 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i3…
118 %tmp7 = shufflevector <4 x i32> %tmp6, <4 x i32> undef, <4 x i32> zeroinitializer
124 define <8 x i8> @test11(<16 x i8> %tmp6) nounwind {
126 ; CHECK-NEXT: shufflevector <16 x i8> %tmp6, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3…
[all …]
Dbswap.ll23 %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
26 %tmp10 = or i32 %tmp6, %tmp9 ; <i32> [#uses=1]
55 %tmp6 = bitcast i16 %tmp.upgrd.3 to i16 ; <i16> [#uses=1]
56 %tmp6.upgrd.4 = zext i16 %tmp6 to i32 ; <i32> [#uses=1]
57 %retval = trunc i32 %tmp6.upgrd.4 to i16 ; <i16> [#uses=1]
70 %tmp6 = lshr i32 %x, 24 ; <i32> [#uses=1]
71 %tmp7 = or i32 %tmp5, %tmp6 ; <i32> [#uses=1]
Dand-xor-merge.ll7 %tmp6 = and i32 %z, %y
8 %tmp7 = xor i32 %tmp3, %tmp6
15 %tmp6 = or i32 %y, %x
16 %tmp7 = xor i32 %tmp3, %tmp6
/external/llvm/test/Transforms/IndVarSimplify/
Div-fold.ll17 %tmp6 = load i32* %arrayidx, align 4
21 %tmp6.1 = load i32* %arrayidx.1, align 4
27 %r = add i32 %tmp6, %tmp6.1
44 %tmp6 = load i32* %arrayidx, align 4
48 %tmp6.1 = load i32* %arrayidx.1, align 4
54 %r = add i32 %tmp6, %tmp6.1
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-uxtb.ll47 %tmp6 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
48 ret i32 %tmp6
74 %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
75 ret i32 %tmp6
89 %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
90 ret i32 %tmp6
103 %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
104 ret i32 %tmp6
117 %tmp6 = or i32 %tmp5, %tmp1 ; <i32> [#uses=1]
118 ret i32 %tmp6

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