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Searched refs:writeback (Results 1 – 25 of 32) sorted by relevance

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/external/clang/lib/CodeGen/
DCGCall.h84 Writeback writeback; in addWriteback() local
85 writeback.Address = address; in addWriteback()
86 writeback.AddressType = addressType; in addWriteback()
87 writeback.Temporary = temporary; in addWriteback()
88 Writebacks.push_back(writeback); in addWriteback()
DCGCall.cpp1581 const CallArgList::Writeback &writeback) { in emitWriteback() argument
1582 llvm::Value *srcAddr = writeback.Address; in emitWriteback()
1601 llvm::Value *value = CGF.Builder.CreateLoad(writeback.Temporary); in emitWriteback()
1609 QualType srcAddrType = writeback.AddressType; in emitWriteback()
/external/llvm/test/MC/ARM/
Dthumb-diagnostics.s41 @ Invalid writeback and register lists for LDM
48 @ CHECK-ERRORS: error: writeback operator '!' expected
51 @ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
56 @ Invalid writeback and register lists for PUSH/POP
67 @ Invalid writeback and register lists for STM
/external/llvm/lib/Target/MBlaze/
DMBlazeSchedule5.td102 // and the destination register is ready after the writeback stage.
129 // results are ready after the writeback stage.
144 // results are ready after the writeback stage.
159 // stage and the results are ready after the writeback stage.
173 // stage and the results are ready after the writeback stage.
187 // results are ready after the writeback stage.
257 // stage and the result is ready after the writeback stage.
/external/oprofile/events/arm/armv6/
Devents14 event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for ever…
/external/oprofile/events/i386/p4/
Dunit_masks44 0x400 writeback lookup from DAC misses 2nd level cache
63 0x02 rte bit 1: 00=read, 01=read invalidate, 10=write, 11=writeback
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1442 bool writeback = (P == 0) || (W == 1); in DecodeAddrMode2IdxInstruction() local
1444 if (P && writeback) in DecodeAddrMode2IdxInstruction()
1446 else if (!P && writeback) in DecodeAddrMode2IdxInstruction()
1449 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1544 bool writeback = (W == 1) | (P == 0); in DecodeAddrMode3Instruction() local
1566 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
1580 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
1597 if (!type && writeback && Rn == 15) in DecodeAddrMode3Instruction()
1599 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
1614 if (!type && writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
[all …]
/external/oprofile/events/avr32/
Devents23 event:0x14 counters:1,2 um:zero minimum:500 name:DCACHE_WB : data cache line writeback
/external/oprofile/events/arm/xscale2/
Devents15 event:0x0c counters:1,2,3,4 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for …
/external/oprofile/events/arm/xscale1/
Devents15 event:0x0c counters:1,2 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for ever…
/external/oprofile/events/i386/p4-ht/
Dunit_masks44 0x400 writeback lookup from DAC misses 2nd level cache
/external/oprofile/events/mips/sb1/
Devents48 event:0xd counters:1,2,3 um:zero minimum:500 name:VICTIM_WRITEBACK :A writeback occurs due to repla…
/external/qemu/
Darm-dis.c3455 bfd_boolean writeback = false, postind = false; in print_insn_thumb32() local
3485 writeback = true; in print_insn_thumb32()
3490 writeback = true; in print_insn_thumb32()
3514 func (stream, writeback ? "]!" : "]"); in print_insn_thumb32()
Dqemu-options.hx94 " [,cache=writethrough|writeback|none][,format=f][,serial=s]\n"
122 @var{cache} is "none", "writeback", or "writethrough" and controls how the host cache is used to ac…
139 corruption. When using the @option{-snapshot} option, writeback caching is
148 @option{cache=writeback} should be used with qcow2. By default, if no explicit
149 caching is specified for a qcow2 disk image, @option{cache=writeback} will be
/external/oprofile/events/i386/atom/
Devents46 event:0x67 counters:0,1 um:core,agent minimum:500 name:BUS_TRANS_WB : Explicit writeback bus transa…
/external/oprofile/events/i386/westmere/
Dunit_masks171 0x10 l1d_wb L1D writeback to L2 transactions
173 0x40 wb L2 writeback to LLC transactions
/external/oprofile/events/x86-64/hammer/
Devents61 event:0x7f counters:0,1,2,3 um:l2_fill minimum:500 name:L2_CACHE_FILL_WRITEBACK : L2 fill/writeback
/external/oprofile/events/x86-64/family11h/
Devents61 event:0x7f counters:0,1,2,3 um:l2_fill minimum:500 name:L2_CACHE_FILL_WRITEBACK : L2 fill/writeback
/external/oprofile/events/i386/nehalem/
Dunit_masks332 0x10 l1d_wb Counts L1D writeback operations to the L2
333 0x20 fill Counts L2 cache line fill operations due to load, RFO, L1D writeback or prefetch
334 0x40 wb Counts L2 writeback operations to the LLC
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td615 // ...with address register writeback:
769 // ...with address register writeback:
832 // ...with address register writeback:
891 // ...with address register writeback:
1016 // ...with address register writeback:
1079 // ...with address register writeback:
1150 // ...with address register writeback:
1227 // ...with address register writeback:
1306 // ...with address register writeback:
1377 // ...with address register writeback:
[all …]
DARMInstrVFP.td125 let Inst{21} = 0; // No writeback
153 let Inst{21} = 0; // No writeback
/external/oprofile/events/i386/core/
Devents55 event:0x67 counters:0,1 um:xc0 minimum:500 name:BUS_TRAN_WB : number of completed writeback transac…
/external/oprofile/events/i386/core_2/
Devents64 …um:core_and_bus_agents minimum:500 name:BUS_TRAN_WB : number of explicit writeback bus transactions
/external/oprofile/events/x86-64/family10/
Devents79 event:0x7f counters:0,1,2,3 um:l2_fill minimum:500 name:L2_CACHE_FILL_WRITEBACK : L2 fill/writeback
/external/oprofile/events/ppc64/power6/
Devents543 …:1 um:zero minimum:1000 name:PM_VMX0_LD_WRBACK_GRP87 : (Group 87 pm_vmx3) VMX0 load writeback valid
545 …:3 um:zero minimum:1000 name:PM_VMX1_LD_WRBACK_GRP87 : (Group 87 pm_vmx3) VMX1 load writeback valid
992 …m:1000 name:PM_MRK_VMX0_LD_WRBACK_GRP162 : (Group 162 pm_mrk_vmx2) Marked VMX0 load writeback valid
993 …m:1000 name:PM_MRK_VMX1_LD_WRBACK_GRP162 : (Group 162 pm_mrk_vmx2) Marked VMX1 load writeback valid

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