Lines Matching refs:u32
20 u32 pbuf; /* physical address of data buffer */
21 u32 cntinfo; /* counter and info bits */
33 u32 pnext; /* paddr of next hpc_dma_desc if any */
38 volatile u32 pbdma_bptr; /* pbus dma channel buffer ptr */
39 volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */
40 u32 _unused0[0x1000/4 - 2]; /* padding */
41 volatile u32 pbdma_ctrl; /* pbus dma channel control register has
58 u32 _unused1[0x1000/4 - 1]; /* padding */
63 volatile u32 cbptr; /* current dma buffer ptr, diagnostic use only */
64 volatile u32 ndptr; /* next dma descriptor ptr */
65 u32 _unused0[0x1000/4 - 2]; /* padding */
66 volatile u32 bcd; /* byte count info */
71 volatile u32 ctrl; /* control register */
81 volatile u32 gfptr; /* current GIO fifo ptr */
82 volatile u32 dfptr; /* current device fifo ptr */
83 volatile u32 dconfig; /* DMA configuration register */
95 volatile u32 pconfig; /* PIO configuration register */
105 u32 _unused1[0x1000/4 - 6]; /* padding */
111 volatile u32 rx_cbptr; /* current dma buffer ptr, diagnostic use only */
112 volatile u32 rx_ndptr; /* next dma descriptor ptr */
113 u32 _unused0[0x1000/4 - 2]; /* padding */
114 volatile u32 rx_bcd; /* byte count info */
119 volatile u32 rx_ctrl; /* control register */
128 volatile u32 rx_gfptr; /* current GIO fifo ptr */
129 volatile u32 rx_dfptr; /* current device fifo ptr */
130 u32 _unused1; /* padding */
131 volatile u32 reset; /* reset register */
136 volatile u32 dconfig; /* DMA configuration register */
146 volatile u32 pconfig; /* PIO configuration register */
152 u32 _unused2[0x1000/4 - 8]; /* padding */
155 volatile u32 tx_cbptr; /* current dma buffer ptr, diagnostic use only */
156 volatile u32 tx_ndptr; /* next dma descriptor ptr */
157 u32 _unused3[0x1000/4 - 2]; /* padding */
158 volatile u32 tx_bcd; /* byte count info */
165 volatile u32 tx_ctrl; /* control register */
173 volatile u32 tx_gfptr; /* current GIO fifo ptr */
174 volatile u32 tx_dfptr; /* current device fifo ptr */
175 u32 _unused4[0x1000/4 - 4]; /* padding */
191 u32 _unused0[0x18000/4];
200 volatile u32 istat0; /* Irq status, only bits <4:0> reliable. */
205 volatile u32 gio_misc; /* GIO misc control bits. */
209 u32 eeprom; /* EEPROM data reg. */
216 volatile u32 istat1; /* Irq status, only bits <9:5> reliable. */
217 volatile u32 bestat; /* Bus error interrupt status reg. */
223 u32 _unused1[0x14000/4 - 5]; /* padding */
226 volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */
227 u32 _unused2[0x7c00/4];
228 volatile u32 scsi1_ext[256]; /* SCSI channel 1 external regs */
229 u32 _unused3[0x7c00/4];
230 volatile u32 eth_ext[320]; /* Ethernet external registers */
231 u32 _unused4[0x3b00/4];
234 volatile u32 pbus_extregs[16][256];
235 volatile u32 pbus_dmacfg[8][128];
265 volatile u32 pbus_piocfg[16][64];
290 volatile u32 pbus_promwe; /* PROM write enable register */
293 u32 _unused5[0x0800/4 - 1];
294 volatile u32 pbus_promswap; /* Chip select swap reg */
297 u32 _unused6[0x0800/4 - 1];
298 volatile u32 pbus_gout; /* PROM general purpose output reg */
301 u32 _unused7[0x1000/4 - 1];
302 volatile u32 rtcregs[14]; /* Dallas clock registers */
303 u32 _unused8[50];
304 volatile u32 bbram[8192-50-14]; /* Battery backed ram */