72       unsigned VirtReg;         // Virtual register number.  member
78         : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {}  in LiveReg()
81         return TargetRegisterInfo::virtReg2Index(VirtReg);  in getSparseSetIndex()
150     int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
155     void killVirtReg(unsigned VirtReg);
157     void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
163     LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {  in findLiveVirtReg()  argument
164       return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));  in findLiveVirtReg()
166     LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const {  in findLiveVirtReg()
167       return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));  in findLiveVirtReg()
173                                        unsigned VirtReg, unsigned Hint);
175                                        unsigned VirtReg, unsigned Hint);
185 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {  in getStackSpaceFor()  argument
187   int SS = StackSlotForVirtReg[VirtReg];  in getStackSpaceFor()
196   StackSlotForVirtReg[VirtReg] = FrameIdx;  in getStackSpaceFor()
231   assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &&  in killVirtReg()
240 void RAFast::killVirtReg(unsigned VirtReg) {  in killVirtReg()  argument
241   assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&  in killVirtReg()
243   LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);  in killVirtReg()
250 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {  in spillVirtReg()  argument
251   assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&  in spillVirtReg()
253   LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);  in spillVirtReg()
262   assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping");  in spillVirtReg()
269     DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)  in spillVirtReg()
271     const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);  in spillVirtReg()
272     int FI = getStackSpaceFor(LRI->VirtReg, RC);  in spillVirtReg()
281       LiveDbgValueMap[LRI->VirtReg];  in spillVirtReg()
393   switch (unsigned VirtReg = PhysRegState[PhysReg]) {  in definePhysReg()  local
397     spillVirtReg(MI, VirtReg);  in definePhysReg()
409     switch (unsigned VirtReg = PhysRegState[Alias]) {  in definePhysReg()  local
413       spillVirtReg(MI, VirtReg);  in definePhysReg()
436   switch (unsigned VirtReg = PhysRegState[PhysReg]) {  in calcSpillCost()  local
442     DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding "  in calcSpillCost()
446     LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);  in calcSpillCost()
459     switch (unsigned VirtReg = PhysRegState[Alias]) {  in calcSpillCost()  local
468       LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);  in calcSpillCost()
484   DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to "  in assignVirtToPhysReg()
486   PhysRegState[PhysReg] = LR.VirtReg;  in assignVirtToPhysReg()
492 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {  in assignVirtToPhysReg()  argument
493   LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);  in assignVirtToPhysReg()
503   const unsigned VirtReg = LRI->VirtReg;  in allocVirtReg()  local
505   assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&  in allocVirtReg()
508   const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);  in allocVirtReg()
524       return assignVirtToPhysReg(VirtReg, Hint);  in allocVirtReg()
539   DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "  in allocVirtReg()
561     return assignVirtToPhysReg(VirtReg, BestReg);  in allocVirtReg()
567   return assignVirtToPhysReg(VirtReg, *AO.begin());  in allocVirtReg()
573                       unsigned VirtReg, unsigned Hint) {  in defineVirtReg()  argument
574   assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&  in defineVirtReg()
578   tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));  in defineVirtReg()
582         MRI->hasOneNonDBGUse(VirtReg)) {  in defineVirtReg()
583       const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);  in defineVirtReg()
606                       unsigned VirtReg, unsigned Hint) {  in reloadVirtReg()  argument
607   assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&  in reloadVirtReg()
611   tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));  in reloadVirtReg()
615     const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);  in reloadVirtReg()
616     int FrameIndex = getStackSpaceFor(VirtReg, RC);  in reloadVirtReg()
617     DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into "  in reloadVirtReg()
877            assert(TargetRegisterInfo::isVirtualRegister(i->VirtReg) &&  in AllocateBasicBlock()
881            assert(PhysRegState[i->PhysReg] == i->VirtReg && "Bad inverse map");  in AllocateBasicBlock()