Lines Matching refs:VirtReg
137 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage()
138 return ExtraRegInfo[VirtReg.reg].Stage; in getStage()
141 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
143 ExtraRegInfo[VirtReg.reg].Stage = Stage; in setStage()
354 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg() argument
355 if (VRM->hasPhys(VirtReg)) { in LRE_CanEraseVirtReg()
356 Matrix->unassign(LIS->getInterval(VirtReg)); in LRE_CanEraseVirtReg()
364 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg() argument
365 if (!VRM->hasPhys(VirtReg)) in LRE_WillShrinkVirtReg()
369 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
438 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign() argument
444 if (!Matrix->checkInterference(VirtReg, PhysReg)) in tryAssign()
453 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg)) in tryAssign()
457 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) { in tryAssign()
458 evictInterference(VirtReg, Hint, NewVRegs); in tryAssign()
472 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost); in tryAssign()
515 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference() argument
518 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg) in canEvictInterference()
528 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade; in canEvictInterference()
534 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in canEvictInterference()
553 bool Urgent = !VirtReg.isSpillable() && in canEvictInterference()
555 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) < in canEvictInterference()
575 if (!Urgent && !shouldEvict(VirtReg, IsHint, *Intf, BreaksHint)) in canEvictInterference()
586 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference() argument
591 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade; in evictInterference()
593 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++; in evictInterference()
601 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in evictInterference()
615 VirtReg.isSpillable() < Intf->isSpillable()) && in evictInterference()
627 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, in tryEvict() argument
641 BestCost.MaxWeight = VirtReg.weight; in tryEvict()
658 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost)) in tryEvict()
672 evictInterference(VirtReg, BestPhys, NewVRegs); in tryEvict()
1099 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryRegionSplit() argument
1191 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this); in tryRegionSplit()
1234 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryBlockSplit() argument
1236 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed"); in tryBlockSplit()
1237 unsigned Reg = VirtReg.reg; in tryBlockSplit()
1239 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this); in tryBlockSplit()
1286 RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryInstructionSplit() argument
1289 if (!RegClassInfo.isProperSubClass(MRI->getRegClass(VirtReg.reg))) in tryInstructionSplit()
1294 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this); in tryInstructionSplit()
1323 DebugVars->splitRegister(VirtReg.reg, LREdit.regs()); in tryInstructionSplit()
1420 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryLocalSplit() argument
1447 if (Matrix->checkRegMaskInterference(VirtReg)) { in tryLocalSplit()
1492 bool ProgressRequired = getStage(VirtReg) >= RS_Split2; in tryLocalSplit()
1509 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg)) in tryLocalSplit()
1604 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this); in tryLocalSplit()
1613 DebugVars->splitRegister(VirtReg.reg, LREdit.regs()); in tryLocalSplit()
1643 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order, in trySplit() argument
1646 if (getStage(VirtReg) >= RS_Spill) in trySplit()
1650 if (LIS->intervalIsInOneMBB(VirtReg)) { in trySplit()
1652 SA->analyze(&VirtReg); in trySplit()
1653 unsigned PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs); in trySplit()
1656 return tryInstructionSplit(VirtReg, Order, NewVRegs); in trySplit()
1661 SA->analyze(&VirtReg); in trySplit()
1670 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) in trySplit()
1677 if (getStage(VirtReg) < RS_Split2) { in trySplit()
1678 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs); in trySplit()
1684 return tryBlockSplit(VirtReg, Order, NewVRegs); in trySplit()
1692 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit() argument
1695 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo); in selectOrSplit()
1696 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) in selectOrSplit()
1699 LiveRangeStage Stage = getStage(VirtReg); in selectOrSplit()
1701 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n'); in selectOrSplit()
1707 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs)) in selectOrSplit()
1716 setStage(VirtReg, RS_Split); in selectOrSplit()
1718 NewVRegs.push_back(&VirtReg); in selectOrSplit()
1724 if (Stage >= RS_Done || !VirtReg.isSpillable()) in selectOrSplit()
1728 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs); in selectOrSplit()
1734 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this); in selectOrSplit()