271     unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());  in getVR()  local
274     if (!VReg) {  in getVR()
276       VReg = MRI->createVirtualRegister(RC);  in getVR()
279             TII->get(TargetOpcode::IMPLICIT_DEF), VReg);  in getVR()
280     return VReg;  in getVR()
302   unsigned VReg = getVR(Op, VRBaseMap);  in AddRegisterOperand()  local
303   assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");  in AddRegisterOperand()
319     if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {  in AddRegisterOperand()
322               TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);  in AddRegisterOperand()
323       VReg = NewVReg;  in AddRegisterOperand()
348   MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,  in AddRegisterOperand()
429 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,  in ConstrainForSubReg()  argument
431   const TargetRegisterClass *VRC = MRI->getRegClass(VReg);  in ConstrainForSubReg()
437     RC = MRI->constrainRegClass(VReg, RC, MinRCSize);  in ConstrainForSubReg()
441     return VReg;  in ConstrainForSubReg()
449     .addReg(VReg);  in ConstrainForSubReg()
483     unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);  in EmitSubregNode()  local
484     MachineInstr *DefMI = MRI->getVRegDef(VReg);  in EmitSubregNode()
503       VReg = ConstrainForSubReg(VReg, SubIdx,  in EmitSubregNode()
513               TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);  in EmitSubregNode()
576   unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);  in EmitCopyToRegClassNode()  local
584     NewVReg).addReg(VReg);  in EmitCopyToRegClassNode()